광학 메타물질에서의 광파 전달 특성에 대한 연구

Thesis(doctors) --서울대학교 대학원 :전기· 컴퓨터공학부,2009.8.Docto

Low-Power High-Speed Transceivers with Channel-Swing of 40mV for TSV and PCB Channels

DoctorTwo transceiver circuits are proposed for low-power high-speed transmission by reducing the channel-signal-swing to 40mV; one is a single-ended transceiver circuit for an on-chip through-silicon via (TSV) channel and the other is a differential transceiver circuit for a 12” FR-4 channel. First, the single-ended transceiver circuit for on-chip TSV channel employs a switched-diode termination (SDT). The channel signal swing is limited to 40 mV by the SDT to reduce the transmitter (TX) power without short-circuit current loss of the center-tap resistor termination. An inverter-cascade amplifier is used to reduce the receiver (RX) power. Inverter feedback is applied to the cascade amplifier of the RX to increase the bandwidth from 0.9 to 5.0 GHz. The transceiver in the 65-nm CMOS process combined with an emulated five-stack TSV on the same chip works at 8 Gb/s with 149 fJ/b/pF and a 1.2-V supply. Second, the differential transceiver circuit has 40mVppd channel signal-swing, 9mVppd receiver (RX) input sensitivity, and 0.59pJ/b energy efficiency at 9Gb/s with a 12” FR-4 channel. A current-integrating TIA (CI-TIA) is used as a RX pre-amplifier to enhance the RX input sensitivity by increasing the voltage gain of the CI-TIA to around 18 at 9Gb/s. A voltage-mode pre-emphasis equalizer is combined with a current-mode logic (CML) driver at transmitter (TX) to save the low-frequency de-emphasis current of the conventional current-mode equalizer combined with a CML driver. The voltage-mode equalizer consists of a series connection of an inverter and a capacitor; the equalization coefficient is proportional to the supply voltage of the inverter. The transceiver chip in a 65nm CMOS process consumes 2.8mW at TX and 2.5mW at RX with a 1V supply and a 12” FR-4 channel at 9Gb/s

An On-chip TSV Emulation Using Metal Bar Surrounded by Metal Ring to Develop Interface Circuits

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광섬유 스펙클 패턴 분석을 이용한 파장 센서의 연구

학위논문(석사)--서울대학교 대학원 :전기공학부,2000.Maste

시그마-SPICE: 멀티 코어 CPU용 병렬 모드 회로 시뮬레이션 프로그램

MasterSIGMA-SPICE, which is based on SPICE3, is improved to include the Monte Carlo simulation feature for statistical circuit simulation. Also, the parallel Monte Carlo simulation is proposed by employing the parallel computing cluster method. Examples of PLL circuits are used for the verification of the simulator.Using multi-thread generated by OpenMP, a parallel mode SPICE simulation method is added in SIGMA-SPICE. Also, the simulation with multi-core CPU is enabled. Examples of transmitter (TX) circuit and USB2.0 analog circuit are used for the verification of the simulator

An On-chip TSV Emulation Using Metal Bar Surrounded by Metal Ring to Develop Interface Circuits

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시그마-SPICE : 멀티 코어 CPU용 병렬 모드 SPICE

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시그마-SPICE : SPICE3 기반의 혼성모드 및 병렬 몬테카를로 회로 시뮬레이터

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A SPICE3-based mixed-mode and parallel Monte Carlo circuit simulator

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A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS

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