High Speed Data Processing Unit Development Using Xilinx GTP Interface and DDR-2 Memory

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.저잡음 고속데이터 처리장치 성능 시뮬레이터 개