An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement

In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs that utilize delay lines. Additionally, this generic method allows for trade-offs between resolution, linearity, and resource utilization. Since nonlinearity is one of the predominant issues regarding delay lines in FPGA-based TDCs, combined with the fact that delay lines are utilized for a wide range of TDC architectures (not limited to the delay-line TDC), other implementations (e.g., Vernier or wave union TDCs), also in different FPGA devices, can directly benefit from the proposed adaptive method, with no need for either custom routing or complex tuning of the converter. Furthermore, implementation-related challenges regarding clock skew, measurement uncertainty, and the placement of the TDC are discussed and we also propose an experimental setup that utilizes only FPGA resources in order to characterize the converter. Although the TDC in this work was implemented in a Xilinx Virtex-6 device and was characterized under different operational modes, we successfully optimized the converter’s nonlinearity and resource utilization while retaining single-shot precision. The best performing (in terms of linearity) implementation reached DNLrms and INLrms values of 0.30 LSB and 0.45 LSB, respectively, and the single-shot precision (σ) was 9.0 ps

HEPATIC HISTOPATHOLOGIC CHANGES IN PATIENTS WITH GALLSTONE DISEASE

THIS STUDY WAS UNDERTAKEN IN AN EFFORT TO ASSESS THE FREQUENCY AND SEVERITY OF LIVER DAMAGE IN 304 PATIENTS WITH GALLSTONE DISEASE AND IN A GROUP OF 30 CONTROL PATIENTS. THE ROLE OF BACTERIA, AS WELL AS THE ROLE OF OTHER CLINICAL AND LABORATORY PARAMETERS INVESTIGATED IN THE DEVELOPMENT OF THESE CHANGES. THE STUDY DEMONSTRATED THAT THE FILTRATION OF PORTAL TRIADS OF LIVER ACCOMPANIED WITH CHRONIC INFLAMMATION, IS MORE COMMON IN PATIENTS WITH GALLSTONE DISEASE, THAN IN CONTROL PATIENTS (P<0,006). PATIENTS WITH PORTAL INFLAMMATION (ACUTE OR CHRONIC)HAVE POSITIVE BILE-CULTURE 50% PER CENT MORE THAN IN PATIENTS WITH NORMAL LIVER BIOPSY. THE FREQUENCY OF POSITIVE BILE CULTURES INCREASED ACCORDING TO THE SEVERITY OF THE BILIARY TRACT-DISEASE. CULTURES OF THE BILIARY TRACT WERE POSITIVE IN 111 OF 304 PATIENTS (36,5%) AND E.COLI WAS THE MOST FREQUENT ORGANISM. THEPOSITIVE BILE CULTURE IS MORE COMMON IN OLD-AGED PATIENTS THAN IN PATIENTS UNDER 65 YEARS OLD (P:0,0003). PATIENTS WITH HEPATIC HISTOPATHOLOGIC CHANGES APPEARED AN INCREASED FREQUENCY OF POST- OPERATIVE COMPLICATIONS (P:0,0004) AND LOTSOF DAYS OF HOSPITAL STAY.ΣΕ ΜΙΑ ΚΛΙΝΙΚΟΕΡΓΑΣΤΗΡΙΑΚΗ ΜΕΛΕΤΗ ΠΟΥ ΔΙΗΡΚΕΣΕ 18 ΜΗΝΕΣ (1985- 1986), ΒΑΣΕΙ ΣΥΓΚΕΚΡΙΜΕΝΟΥ ΠΡΩΤΟΚΟΛΛΟΥ ΜΕΛΕΤΗΘΗΚΕ Η ΣΥΧΝΟΤΗΤΑ ΚΑΙ ΤΟ ΕΙΔΟΣ ΤΩΝ ΠΑΘΟΛΟΓΟΑΝΑΤΟΜΙΚΩΝ ΑΛΛΟΙΩΣΕΩΝ ΤΟΥ ΗΠΑΤΟΣ ΣΕ 304 ΑΣΘΕΝΕΙΣ ΜΕ ΛΙΘΙΑΣΙΚΗ ΝΟΣΟ ΤΩΝ ΧΟΛΗΦΟΡΩΝ ΚΑΙ ΣΕΜΙΑ ΟΜΑΔΑ 30 ΜΑΡΤΥΡΩΝ. ΔΙΕΡΕΥΝΗΘΗΚΕ ΕΠΙΣΗΣ Η ΕΠΙΠΤΩΣΗΣ ΤΗΣ ΜΙΚΡΟΒΙΟΛΟΓΙΑΣ ΣΤΗΝΑΝΑΠΤΥΞΗ ΑΥΤΩΝ ΤΩΝ ΑΛΛΟΙΩΣΕΩΝ ΚΑΙ ΕΡΓΑΣΤΗΡΙΑΚΩΝ ΠΑΡΑΜΕΤΡΩΝ ΣΤΗΝ ΕΜΦΑΝΙΣΗ ΑΥΞΗΜΕΝΗΣ ΣΥΧΝΟΤΗΤΑΣ ΘΕΤΙΚΗΣ ΚΑΛΛΙΕΡΓΕΙΑΣ ΧΟΛΗΣ. Η ΜΕΛΕΤΗ ΑΠΕΔΕΙΞΕ ΟΤΙ Η ΔΙΗΘΗΣΗ ΤΩΝΠΥΛΑΙΩΝ ΔΙΑΣΤΗΜΑΤΩΝ ΤΟΥ ΗΠΑΤΟΣ ΜΕ ΣΤΟΙΧΕΙΑ ΧΡΟΝΙΑΣ ΦΛΕΓΜΟΝΗΣ, ΣΥΝΟΔΕΥΕΙ ΑΣΘΕΝΕΙΣ ΜΕ ΛΙΘΙΑΣΗ ΤΩΝ ΧΟΛΗΦΟΡΩΝ ΣΕ ΣΧΕΣΗ ΣΤΑΤΙΣΤΙΚΑ ΣΗΜΑΝΤΙΚΗ ΜΕ ΤΗΝ ΟΜΑΔΑ ΜΑΡΤΥΡΩΝ(Ρ<0,006). ΑΣΘΕΝΕΙΣ ΜΕ ΠΕΡΙΠΥΛΑΙΑ ΦΛΕΓΜΟΝΗ (ΟΞΕΙΑ 'Η ΧΡΟΝΙΑ) ΕΧΟΥΝ ΘΕΤΙΚΗ ΤΗΝ ΚΑΛΛΙΕΡΓΕΙΑ ΧΟΛΗΣ, ΣΕ ΔΙΠΛΑΣΙΑ ΣΥΧΝΟΤΗΤΑ ΑΠΟ ΑΥΤΟΥΣ ΠΟΥ ΕΧΟΥΝ ΦΥΣΙΟΛΟΓΙΚΗ ΒΙΟΨΙΑ ΗΠΑΤΟΣ. Η ΑΝΑΠΤΥΞΗ ΤΩΝ ΒΑΚΤΗΡΙΩΝ ΣΤΗΝ ΚΑΛΛΙΕΡΓΕΙΑ ΧΟΛΗΣ, ΠΑΡΟΥΣΙΑΖΕΤΑΙ ΜΕ ΑΥΞΑΝΟΜΕΝΗ ΣΥΧΝΟΤΗΤΑ ΑΠΟ ΤΗΝ ΧΡΟΝΙΑ ΧΟΛΟΚΥΣΤΙΤΙΔΑ ΜΕΧΡΙ ΤΗΝ ΟΞΕΙΑ ΦΛΕΓΜΟΝΗ ΚΑΙ ΤΟ ΕΠΕΙΓΟΝ ΧΕΙΡΟΥΡΓΕΙΟ. ΣΥΧΝΟΤΕΡΟ ΒΑΚΤΗΡΙΟ ΑΠΟΜΟΝΩΘΗΚΕ Η E. COLI ΚΑΙ Η ΜΙΚΡΟΒΙΟΛΟΓΙΑ ΑΝΗΛΘΕ ΣΤΟ 36,5% ΤΩΝ ΑΣΘΕΝΩΝ. ΑΣΘΕΝΕΙΣ "ΤΡΙΤΗΣ ΗΛΙΚΙΑΣ" ΕΧΟΥΝ ΣΕ ΣΤΑΤΙΣΤΙΚΩΣΣΗΜΑΝΤΙΚΗ ΣΧΕΣΗ ΘΕΤΙΚΗ ΚΑΛΛΙΕΡΓΕΙΑ ΧΟΛΗΣ ΣΕ ΣΥΓΚΡΙΣΗ ΜΕ ΤΟΥΣ ΑΣΘΕΝΕΙΣ ΚΑΤΩ ΤΩΝ65 ΧΡΟΝΩΝ (Ρ:03). ΥΠΑΡΧΕΙ ΣΤΑΤΙΣΤΙΚΩΣ ΣΗΜΑΝΤΙΚΗ ΣΧΕΣΗ ΜΕΤΑΞΥ ΤΗΣ ΠΑΘΟΛΟΓΙΚΗΣ ΒΙΟΨΙΑΣ ΗΠΑΤΟΣ ΚΑΙ ΤΩΝ ΠΑΘΟΛΟΓΙΚΩΝ ΤΙΜΩΝ ΤΩΝ ΗΠΑΤΙΚΩΝ ΕΝΖΥΜΩΝ (Ρ:0,00005). ΤΕΛΟΣΗ ΑΝΕΥΡΕΣΗ ΠΑΘΟΛΟΓΙΚΗΣ ΒΙΟΨΙΑΣ ΗΠΑΤΟΣ ΣΥΝΟΔΕΥΕΤΑΙ ΣΕ ΠΟΛΥ ΣΗΜΑΝΤΙΚΟ ΒΑΘΜΟ ΜΕ ΤΗΝ ΕΜΦΑΝΙΣΗ ΜΕΤΕΓΧΕΙΡΗΤΙΚΩΝ ΕΠΙΠΛΟΚΩΝ (P<0,0004) ΚΑΙ ΜΕ ΠΑΡΑΤΕΤΑΜΕΝΟ ΧΡΟΝΟ ΝΟΣΗΛΕΙΑΣ

An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications

Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.</jats:p

An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications

Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype&rsquo;s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research