Stream Productivity by Outermost Termination

Streams are infinite sequences over a given data type. A stream specification is a set of equations intended to define a stream. A core property is productivity: unfolding the equations produces the intended stream in the limit. In this paper we show that productivity is equivalent to termination with respect to the balanced outermost strategy of a TRS obtained by adding an additional rule. For specifications not involving branching symbols balancedness is obtained for free, by which tools for proving outermost termination can be used to prove productivity fully automatically

Loops under Strategies ... Continued

While there are many approaches for automatically proving termination of term rewrite systems, up to now there exist only few techniques to disprove their termination automatically. Almost all of these techniques try to find loops, where the existence of a loop implies non-termination of the rewrite system. However, most programming languages use specific evaluation strategies, whereas loop detection techniques usually do not take strategies into account. So even if a rewrite system has a loop, it may still be terminating under certain strategies. Therefore, our goal is to develop decision procedures which can determine whether a given loop is also a loop under the respective evaluation strategy. In earlier work, such procedures were presented for the strategies of innermost, outermost, and context-sensitive evaluation. In the current paper, we build upon this work and develop such decision procedures for important strategies like leftmost-innermost, leftmost-outermost, (max-)parallel-innermost, (max-)parallel-outermost, and forbidden patterns (which generalize innermost, outermost, and context-sensitive strategies). In this way, we obtain the first approach to disprove termination under these strategies automatically.Comment: In Proceedings IWS 2010, arXiv:1012.533

Schuldnerschutz bei fehlender Zustellung eines EU-Mahnbescheids: Regelungslücken der EuMahnVO : (AG Wedding, 22.10.2014 - 70b C 17/14, unten S. 420, Nr. 40)

Regulation 1896/2006 does not provide for effective debtor protection in cases when a European Order for Payment was not properly served on the debtor. As a result of the unilateral nature of the procedure for issuing the order, the order will be declared enforceable if the defendant does not challenge it within a period of 30 days. However, the service of the payment order shall safeguard the right to a defense. When the defendant has never been informed about the ongoing procedure, he should be able to easily contest the Order for Payment even after it has been declared enforceable. Yet, the text of the Regulation does not provide for a remedy in this situation. In a reference for a preliminary ruling, the Local Court Berlin-Wedding asked the European Court of Justice which remedy should apply. The referring court suggested an application by analogy of the review proceedings provided for in Article 20 of Regulation 1896/2006 in order to ensure an effective right to a defense. Regrettably, the CJEU did not endorse this solution. It declared national procedural law applicable in accordance with Article 26 of the Regulation. As a consequence, parties are sent to the fragmented remedies of national procedural laws. As the efficiency and uniform application of Regulation 1896/2006 is no longer guaranteed, the European lawmaker is called to remedy the insufficient situation. This article addresses the final decision of the Local Court which implemented the CJEU’s judgment

Symbolic power analysis of cell libraries

Cell libraries are collections of logic cores (cells) used to construct larger chip designs; hence, any reduction in their power consumption may have a major impact in the power consumption of larger designs. The power consumption of a cell is often determined by triggering it with all possible input values in all possible orders at each state. In this paper, we first present a technique to measure the power consumption of a cell more efficiently by reducing the number of input orders that have to be checked. This is based on symbolic techniques and analyzes the number of (weighted) wire chargings taking place. Additionally, we present a technique that computes for a cell all orders that lead to the same state, but differ in their power consumption. Such an analysis is used to select the orders that minimize the required power, without affecting functionality, by inserting sufficient delays. Both techniques have been evaluated on an industrial cell library and were able to efficiently reduce the number of orders needed for power characterization and to efficiently compute orders that consume less power for a given state and input-vector transition

Formal analysis of non-determinism in Verilog cell library simulation models

Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve non-determinism, which in turn, poses a challenge to their validation. Simulators often resolve such problems by using certain rules to make the specification deterministic. This however is not justified by the behavior of the hardware that is to be modeled. Hence, simulation might not be able to detect certain errors. In this paper we develop a technique to prove whether non-determinism does not affect the behavior of the simulation model, or whether there exists a situation in which the simulation model might produce different results. To make our technique efficient, we show that the global property of equal behavior for all possible evaluations is equivalent to checking only a certain local property