As Ethiopia works towards becoming a middle income country, can it tackle growing inequality?

LSE alumnus Bashir Ali reflects on the contrast between the economic miracle and growing inequality in Ethiopia

Twenty five years later, Somaliland comes of age

LSE alumnus Bashir Ali reflects on Somaliland’s progress and development as it celebrates a landmark anniversary

The Void

Translation of a story by novelist, playwright and short story writer, Ali Mohammad Lone, born in 1927 in Srinagar, Jammu and Kashmir, India. He worked as Assistant Producer in Radio Kashmir, and as Deputy Secretary of Cultural Academy of Jammu and Kashmir. He began his literary career by writing in Urdu but soon turned to his mother tongue Kashmiri. Lone has authored many novels, plays and short stories. Asi Ti Chi Insaan (We Too Are Humans) is his famous novel in Kashmiri. His play Suyya, which has been translated in a number of Indian languages, bagged the prestigious Sahitya Akademi Award in 1972. Lone has also translated Maxim Gorky’s famous novel Mother into Kashmiri. He has been honoured with Soviet Land Nehru Award. Though influenced by left-oriented Progressive Writers’ Movement in India, Lone skilfully uses modernist elements in his work. He died in an accident on 22 December 1987 while returning home in Indira Nagar, Srinagar

Data Visualization Using Rational Trigonometric Spline

This paper describes the use of trigonometric spline to visualize the given planar data. The goal of this work is to determine the smoothest possible curve that passes through its data points while simultaneously satisfying the shape preserving features of the data. Positive, monotone, and constrained curve interpolating schemes, by using

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems

Recently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the fault-tolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone

Testing of Level Shifters in Multiple Voltage Designs

The use of multiple voltages for different cores is becoming a widely accepted technique for efficient power management. Level shifters are used as interfaces between voltage domains. Through extensive transistor level simulations of resistive open, bridging and resistive short faults, we have classified the testing of level shifters into PASSIVE and ACTIVE modes. We examine if high test coverage can be achieved in the PASSIVE mode. We consider resistive opens and shorts and show that, for testing purposes, consideration of purely digital fault effects is sufficient. Thus conventional digital DfT can be employed to test level shifters. In all cases, we conclude that using sets of single supply voltages for testing is sufficient