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    Self-similar solutions to coagulation equations with time-dependent tails: the case of homogeneity smaller than one

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    We prove the existence of a one-parameter family of self-similar solutions with time-dependent tails for Smoluchowski's coagulation equation, for a class of rate kernels K(x,y)K(x,y) which are homogeneous of degree γ(,1)\gamma\in(-\infty,1) and satisfy K(x,1)xaK(x,1)\sim x^{-a} as x0x\to 0, for a=1γa=1-\gamma. In particular, for small values of a parameter ρ>0\rho>0 we establish the existence of a positive self-similar solution with finite mass and asymptotics A(t)x(2+ρ)A(t)x^{-(2+\rho)} as xx\to\infty, with A(t)ρtρ1γA(t)\sim\rho t^\frac{\rho}{1-\gamma}

    Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

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    The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This work focussed also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design
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