Comprehensive Study of Process-Induced Device Performance Variability and its Optimization for 14 nm Technology Node Bulk FinFETs

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Electrostatics and Performance Benchmarking using all Types of III-V Multi-Gate FinFETs for sub 7nm Technology Node Logic Application

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Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node

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VLSI Processed InGaAs on Si MOSFETs with Thermally Stable, Self-Aligned Ni-InGaAs Contacts Achieving: Enhanced Drive Current and Pathway Towards a Unified S/D Contact Module

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