In vitro binding of Sorghum bicolor transcription factors ABI4 and ABI5 to a conserved region of a GA 2-OXIDASE promoter: possible role of this interaction in the expression of seed dormancy

The precise adjustment of the timing of dormancy release according to final grain usage is still a challenge for many cereal crops. Grain sorghum [Sorghum bicolor (L.) Moench] shows wide intraspecific variability in dormancy level and susceptibility to pre-harvest sprouting (PHS). Both embryo sensitivity to abscisic acid (ABA) and gibberellin (GA) metabolism play an important role in the expression of dormancy of the developing sorghum grain. In previous works, it was shown that, simultaneously with a greater embryo sensitivity to ABA and higher expression of SbABA-INSENSITIVE 4 (SbABI4) and SbABA-INSENSITIVE 5 (SbABI5), dormant grains accumulate less active GA4 due to a more active GA catabolism. In this work, it is demonstrated that the ABA signalling components SbABI4 and SbABI5 interact in vitro with a fragment of the SbGA 2-OXIDASE 3 (SbGA2ox3) promoter containing an ABA-responsive complex (ABRC). Both transcription factors were able to bind the promoter, although not simultaneously, suggesting that they might compete for the same cis-acting regulatory sequences. A biological role for these interactions in the expression of dormancy of sorghum grains is proposed: either SbABI4 and/or SbABI5 activate transcription of the SbGA2ox3 gene in vivo and promote SbGA2ox3 protein accumulation; this would result in active degradation of GA4, thus preventing germination of dormant grains. A comparative analysis of the 5′-regulatory region of GA2oxs from both monocots and dicots is also presented; conservation of the ABRC in closely related GA2oxs from Brachypodium distachyon and rice suggest that these species might share the same regulatory mechanism as proposed for grain sorghum.Fil: Cantoro, Renata. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Parque Centenario. Instituto de Investigaciones Fisiológicas y Ecológicas Vinculadas A la Agricultura; Argentina. Universidad de Buenos Aires. Facultad de Agronomía. Departamento de Producción Vegetal. Cátedra de Cultivos Industriales; ArgentinaFil: Crocco, Carlos Daniel. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Parque Centenario. Instituto de Investigaciones Fisiológicas y Ecológicas Vinculadas A la Agricultura; ArgentinaFil: Benech-arnold, Roberto Luis. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Parque Centenario. Instituto de Investigaciones Fisiológicas y Ecológicas Vinculadas A la Agricultura; Argentina. Universidad de Buenos Aires. Facultad de Agronomía. Departamento de Producción Vegetal. Cátedra de Cultivos Industriales; ArgentinaFil: Rodríguez, María Verónica. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Parque Centenario. Instituto de Investigaciones Fisiológicas y Ecológicas Vinculadas A la Agricultura; Argentin

New techniques for functional testing of microprocessor based systems

Electronic devices may be affected by failures, for example due to physical defects. These defects may be introduced during the manufacturing process, as well as during the normal operating life of the device due to aging. How to detect all these defects is not a trivial task, especially in complex systems such as processor cores. Nevertheless, safety-critical applications do not tolerate failures, this is the reason why testing such devices is needed so to guarantee a correct behavior at any time. Moreover, testing is a key parameter for assessing the quality of a manufactured product. Consolidated testing techniques are based on special Design for Testability (DfT) features added in the original design to facilitate test effectiveness. Design, integration, and usage of the available DfT for testing purposes are fully supported by commercial EDA tools, hence approaches based on DfT are the standard solutions adopted by silicon vendors for testing their devices. Tests exploiting the available DfT such as scan-chains manipulate the internal state of the system, differently to the normal functional mode, passing through unreachable configurations. Alternative solutions that do not violate such functional mode are defined as functional tests. In microprocessor based systems, functional testing techniques include software-based self-test (SBST), i.e., a piece of software (referred to as test program) which is uploaded in the system available memory and executed, with the purpose of exciting a specific part of the system and observing the effects of possible defects affecting it. SBST has been widely-studies by the research community for years, but its adoption by the industry is quite recent. My research activities have been mainly focused on the industrial perspective of SBST. The problem of providing an effective development flow and guidelines for integrating SBST in the available operating systems have been tackled and results have been provided on microprocessor based systems for the automotive domain. Remarkably, new algorithms have been also introduced with respect to state-of-the-art approaches, which can be systematically implemented to enrich SBST suites of test programs for modern microprocessor based systems. The proposed development flow and algorithms are being currently employed in real electronic control units for automotive products. Moreover, a special hardware infrastructure purposely embedded in modern devices for interconnecting the numerous on-board instruments has been interest of my research as well. This solution is known as reconfigurable scan networks (RSNs) and its practical adoption is growing fast as new standards have been created. Test and diagnosis methodologies have been proposed targeting specific RSN features, aimed at checking whether the reconfigurability of such networks has not been corrupted by defects and, in this case, at identifying the defective elements of the network. The contribution of my work in this field has also been included in the first suite of public-domain benchmark networks

Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques

One key aspect to be considered during device testing is the minimization of the switching activity of the circuit under test (CUT), thus avoiding possible problems stemming from overheating it. But there are also scenarios, where the maximization of certain circuits' modules switching activity could be proven useful (e.g., during Burn-In) in order to exercise the circuit under extreme operating conditions in terms of temperature (and temperature gradients). Resorting to a functional approach based on Software-based Self-test guarantees that the high induced activity cannot damage the CUT nor produce any yield loss. However, the generation of effective suitable test programs remains a challenging task. In this paper, we consider a scenario where the modules to be stressed are sub-modules of a fully pipelined processor. We present a technique, based on an evolutionary approach, able to automatically generate stress test programs, i.e., sequences of instructions achieving a high toggling activity in the target module. With respect to previous approaches, the generated sequences are short and repeatable, thus guaranteeing their easy usability to stress a module (and increase its temperature). The processor we used for our experiments is the Open RISC 1200. Results demonstrate that the proposed method is effective in achieving a high value of sustained toggling activity with short (3 instructions) and repeatable sequences

Identificación de QTL para dormición y análisis molecular de la interacción ABA-GAs en cariopses de sorgo granífero

El objetivo de esta tesis fue contribuir a la dilucidación de los mecanismos moleculares y genéticos que participan en la expresión de la dormición de semillas de cereales, utilizando Sorghum bicolor (L.)Moench como sistema modelo. Para ello se utilizaron dos aproximaciones complementarias: la identificación de QTL para el carácter dormición y la evaluación de la ocurrencia de interacciones in vitro entre componentes de la señalización del ácido abscísico (ABA)y el catabolismo de las giberelinas (GAs), candidatos a tener un rol importante durante la expresión de la dormición en granos de sorgo inmaduros (i.e. antes de madurez fisiológica). Los resultados obtenidos permitieron identificar tres QTL (qDOR-5; qDOR-9 y qDOR-10)que explican una proporción de la variabilidad que se observa en el patrón de expresión de dormición de granos de sorgo maduros (i.e. después de madurez fisiológica). Un análisis in silico de las secuencias abarcadas por estos QTL mostró que ninguno ellos incluye genes considerados como candidatos para dormición de sorgo. En ese sentido, esta tesis aportó nuevas regiones genómicas que contienen genes hasta ahora desconocidos, que serían importantes en la expresión del carácter dormición en granos maduros. Por otra parte, los análisis de unión in vitro realizados mostraron que las proteínas SbABI4 y SbABI5 (componentes de la señalización del ABA)pueden interactuar de manera específica con el ABRC (complejo de respuesta al ABA)del promotor del gen SbGA2ox3, responsable de la degradación de giberelinas activas. Este mecanismo de cross-talk ABA-GAs podría ser uno de los responsables del mantenimiento de la dormición en cariopses inmaduros resistentes al brotado pre-cosecha. Más aún, el ABRC del promotor de SbGA2ox3, involucrado en las interacciones, se encontró además en los promotores de genes GA2ox de otras especies monocotiledóneas como Brachypodium y arroz (Oryza sativa), pero no así en las dicotiledóneas analizadas, sugiriendo que el cross-talk ABA-GAs podría tener lugar en otras especies además de sorgo. Los resultados de esta tesis en forma conjunta aportaron nuevas evidencias acerca del rol preponderante que tienen ciertas regiones del genoma o genes puntuales en la expresión de la dormición tanto en granos maduros como inmaduros de sorgo granífero

A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks

The IEEE 1687 standard introduces several novelties, most notably Reconfigurable Scan Networks (RSNs), i.e., scan chains whose length can change dynamically. These architectures offer important advantages but can result in extremely complex integrity test following traditional structural approaches. In this paper, we will present an innovative approach to RSN test and debug based on the functional features of the standard, which is able to greatly speed up test generation time while guaranteeing a precise fault coverage

Fault-Independent Test-Generation for Software-Based Self-Testing

Software-based self-test (SBST) is being widely used in both manufacturing and in-the-field testing of processor-based devices and Systems-on-Chips. Unfortunately, the stuck-at fault model is increasingly inadequate to match the new and different types of defects in the most recent semiconductor technologies, while the explicit and separate targeting of every fault model in SBST is cumbersome due to the high complexity of the test-generation process, the lack of automation tools, and the high CPU-intensity of the fault-simulation process. Moreover, defects in advanced semiconductor technologies are not always covered by the most commonly used fault-models, and the probability of defect-escapes increases even more. To overcome these shortcomings we propose the first fault-independent SBST method. The proposed method is almost fully automated, it offers high coverage of non-modeled faults by means of a novel SBST-oriented probabilistic metric, and it is very fast as it omits the time-consuming test-generation/fault-simulation processes. Extensive experiments on the OpenRISC OR1200 processor show the advantages of the proposed method

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests

Nowadays many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behaviour, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Postprocessing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploratio

Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects

A widely adopted practice for in-field testing of electronic devices uses Software-Based Self-Test (SBST) in the form of Software Test Libraries (STLs). Typically, STLs target the stuck-at and Transition Delay Fault (TDF) models. However, to face the new defects introduced by the most recent semiconductor technologies, new fault models must be adopted. Small Delay Defects (SDDs) play an increasingly important role in this scenario. Unlike TDFs, SDDs slightly increase the paths’ timing, whose size is not in the same order of magnitude of the clock period. These defects can cause failures during the operational phase if they affect the critical paths. Remarkably, in scan testing the propagation time of a fault is limited, as a fault effect has to reach the scan flip-flops to be detected. However, in functional testing, the fault effect may require several clock cycles before reaching an observable point. Thus, the delay due to the fault cannot be indefinitely long.As there will be the need to move to delay faults when developing STLs, it is important to use the timing information correctly in functional fault simulations. SDDs are the typical choice. In this paper, we implemented a fault grading process for STLs to show how the fault coverage they can achieve changes when the delay defect increases (from SDDs to the extreme case of TDFs). The work uses static timing analysis; although this is known to yield pessimistic results in some cases, it gives a very good indication of the trend in fault coverage as the SDDs approximate TDFs. Differences in fault coverages with respect to the TDF model are highlighted, while an assessment of the effects of multi-cycle delays is also provided

Renaissance Poem Sarca as Aemulatio with Ancient Authors

The aim of this article is to analyse the Renaissance poem Sarca, whose authorship is attributed to the Italian humanist Pietro Bembo, and to indicate the ancient inspirations of the work. The main model for the work is Carmen 64 by Catullus, although the author also refers to other Roman poets. The intertextual relations between Sarca and the hypotexts are presented on various levels. The analysis focuses on showing parallel elements of the setting and takes in consideration the few similarities at the linguistic and stylistic level. Genre-wise Sarca is classified as an epithalamium of an aythiological character. Its characteristics typical of the Renaissance era are also highlighted. The article also brings up the history of the poem and the topic of its attribution, presenting an extensive state of research.The aim of this article is to analyse the Renaissance poem Sarca, whose authorship is attributed to the Italian humanist Pietro Bembo, and to indicate the ancient inspirations of the work. The main model for the work is Carmen 64 by Catullus, although the author also refers to other Roman poets. The intertextual relations between Sarca and the hypotexts are presented on various levels. The analysis focuses on showing parallel elements of the setting and takes in consideration the few similarities at the linguistic and stylistic level. Genre-wise Sarca is classified as an epithalamium of an aythiological character. Its characteristics typical of the Renaissance era are also highlighted. The article also brings up the history of the poem and the topic of its attribution, presenting an extensive state of research

A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC’16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies