FPGA based Optical Two-way Time Transfer for Clock Correction through Dynamic Reconfiguration

Time transfer is essential for global time keeping and it finds its applications in navigation, communication and tracking systems. Accurate measurement of time difference between two systems and its correction is a substantial issue while maintaining a reliable and error free communication channel. Two Way Time Transfer (TWTT) is one such method to achieve time transfer where timestamps are generated and exchanged between two sites.In this theses, we propose an entirely FPGA based transceiver architecture with an on-board digital feedback for the two-way time transfer protocol, to determine the clock offset/error between two independent systems operating at different frequencies and correct it. Digital feedback loop uses the on-board FPGA system clock generated by the MMCM primitive as its reference clock oscillator. Furthermore, a dynamic reconfiguration port(DRP) is designed to wrap the MMCM primitive which allows dynamic reconfiguration. The functionality of the design is evaluated by post implementation simulations and experiments conducted in the laboratory on the optical test setup with a 1 km fiber spool. The designed transceiver is configurable in terms of the data width, transmitter and receiver frequencies. The design can be switched to operate as master or slave and is implemented on Xilinx Virtex�-7 FPGA VC707 Evaluation Kit. The proposed model is capable of maintaining a time error in the range of 200 ns for an oscillator(running at 100 MHz) with a fractional frequency error of 4*103 (Oscilloscope measurement) while the oscillator updates are provided for every 50 us. Given the fact that all the timestamps are exchanged in a serial fashion, channel efficiency is also a metric to be considered. In this work, considering the preamble of 8 bits and timestamps of 64 bits, the channel efficiency of 89% is achieved

Norethindrone Acetate in the Medical Management of Adenomyosis

The role of norethindrone acetate (NA) in the management of adenomyosis was evaluated with a retrospective chart review of 28 premenopausal women between 27–49 years of age presenting with moderate to severe pelvic pain and bleeding. Bleeding and dysmenorrhea scores were analyzed using paired T-tests. There was significant improvement of both dysmenorrhea and bleeding after treatment. Age showed no correlation with dysmenorrhea or bleeding. Low dose NA could be considered an effective, well-tolerated and inexpensive medical alternative to surgery for treating symptomatic adenomyosis. Large multicentric studies may help validate our findings

Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks

IEEE Transactions on Very Large Scale Integration (VLSI) SystemsIn deep convolutional neural networks (DCNNs), model size and computation complexity are two important factors governing throughput and energy efficiency when deployed to hardware for inference. Recent works on compact DCNNs as well as pruning methods are effective, yet with drawbacks. For instance, more than half the size of all MobileNet models lies in their last two layers, mainly because compact separable convolution (CONV) layers are not applicable to their last fully connected (FC) layers. Also, in pruning methods, the compression is gained at the expense of irregularity in the DCNN architecture, which necessitates additional indexing memory to address nonzero weights, thereby increasing memory footprint, decompression delays, and energy consumption. In this article, we propose cyclic sparsely connected (CSC) architectures, with memory/computation complexity of O(N logN) , where N is the number of nodes/channels given a DCNN layer that, contrary to compact depthwise separable layers, can be used as an overlay for both FC and CONV layers of O(N²) . Also, contrary to pruning methods, CSC architectures are structurally sparse and require no indexing due to their cyclic nature. We show that both standard convolution and depthwise convolution layers are special cases of the CSC layers, whose mathematical function, along with FC layers, can be unified into one single formulation and whose hardware implementation can be carried out under one arithmetic logic component. We examine the efficacy of the CSC architectures for compression of LeNet, AlexNet, and MobileNet DCNNs with precision ranging from 2 to 32 bits. More specifically, we surge upon the compact 8-bit quantized 0.5 MobileNet V1 and show that by compressing its last two layers with CSC architectures, the model is compressed by ∼1.5× with a size of only 873 kB and little accuracy loss. Finally, we design a configurable hardware that implements all types of DCNN layers including FC, CONV, depthwise, CSC-FC, and CSC-CONV indistinguishably within a unified pipeline. We implement the hardware on a tiny Xilinx field-programmable gate array (FPGA) for total on-chip processing of the compressed MobileNet that, compared to the related work, has the highest Inference/J while utilizing the smallest FPGA.https://ieeexplore.ieee.org/abstract/document/953790