2,838 research outputs found

    Scalable photonic sources using two-dimensional lead halide perovskite superlattices

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    Miniaturized photonic sources based on semiconducting two-dimensional (2D) materials offer new technological opportunities beyond the modern III-V platforms. For example, the quantum-confined 2D electronic structure aligns the exciton transition dipole moment parallel to the surface plane, thereby outcoupling more light to air which gives rise to high-efficiency quantum optics and electroluminescent devices. It requires scalable materials and processes to create the decoupled multi-quantum-well superlattices, in which individual 2D material layers are isolated by atomically thin quantum barriers. Here, we report decoupled multi-quantum-well superlattices comprised of the colloidal quantum wells of lead halide perovskites, with unprecedentedly ultrathin quantum barriers that screen interlayer interactions within the range of 6.5 Å. Crystallographic and 2D k-space spectroscopic analysis reveals that the transition dipole moment orientation of bright excitons in the superlattices is predominantly in-plane and independent of stacking layer and quantum barrier thickness, confirming interlayer decoupling

    High-performance InSe Transistors with Ohmic Contact Enabled by Nonrectifying-barrier-type Indium Electrodes

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    The electrical contact to two-dimensional (2D)-semiconductor materials are decisive to the electronic performance of 2D-semiconductor field-effect devices (FEDs). The presence of a Schottky barrier often leads to a large contact resistance, which seriously limits the channel conductance and carrier mobility measured in a two-terminal geometry. In contrast, ohmic contact is desirable and can be achieved by the presence of a nonrectifying or tunneling barrier. Here, we demonstrate that an nonrectifying barrier can be realized by contacting indium (In), a low work function metal, with layered InSe because of a favorable band alignment at the In-InSe interface. The nonrectifying barrier is manifested by ohmic contact behavior at T=2 K and a low barrier height, {\Phi}B_B=50 meV. This ohmic contact enables demonstration of an ON-current as large as 410 {\mu}A/{\mu}m, which is among the highest values achieved in FEDs based on layered semiconductors. A high electron mobility of 3,700 and 1,000 cm2^2/Vs is achieved with the two-terminal In-InSe FEDs at T=2 K and room temperature, respectively, which can be attributed to enhanced quality of both conduction channel and the contacts. The improvement in the contact quality is further proven by an X-ray photoelectron spectroscopy study, which suggests that a reduction effect occurs at the In-InSe interface. The demonstration of high-performance In-InSe FEDs indicates a viable interface engineering method for next-generation, 2D-semiconductor-based electronics

    Oscillation-free Quantization for Low-bit Vision Transformers

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    Weight oscillation is an undesirable side effect of quantization-aware training, in which quantized weights frequently jump between two quantized levels, resulting in training instability and a sub-optimal final model. We discover that the learnable scaling factor, a widely-used de facto\textit{de facto} setting in quantization aggravates weight oscillation. In this study, we investigate the connection between the learnable scaling factor and quantized weight oscillation and use ViT as a case driver to illustrate the findings and remedies. In addition, we also found that the interdependence between quantized weights in query\textit{query} and key\textit{key} of a self-attention layer makes ViT vulnerable to oscillation. We, therefore, propose three techniques accordingly: statistical weight quantization (StatsQ\rm StatsQ) to improve quantization robustness compared to the prevalent learnable-scale-based method; confidence-guided annealing (CGA\rm CGA) that freezes the weights with high confidence\textit{high confidence} and calms the oscillating weights; and query\textit{query}-key\textit{key} reparameterization (QKR\rm QKR) to resolve the query-key intertwined oscillation and mitigate the resulting gradient misestimation. Extensive experiments demonstrate that these proposed techniques successfully abate weight oscillation and consistently achieve substantial accuracy improvement on ImageNet. Specifically, our 2-bit DeiT-T/DeiT-S algorithms outperform the previous state-of-the-art by 9.8% and 7.7%, respectively. Code and models are available at: https://github.com/nbasyl/OFQ.Comment: Proceedings of the 40 th International Conference on Machine Learning, Honolulu, Hawaii, USA. PMLR 202, 202

    Team Quotients, Resilience, and Performance of Software Development Projects

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    Past studies have examined actions and strategies that software project teams can take to reduce the negative impact of uncertainties, such as changing requirements. Software development project teams often have to be flexible to follow the pre-defined plans and strive to meet project goals. Sometimes uncertainty may go extreme to temporarily slow projects down and set project teams into reduced productivity. Project teams should be resilient to recover from the reduce productivity condition and move forward toward predefined goals. This study focuses on understanding the importance of team resilience for software project teams and exploring the antecedents of team resilience. Specifically, we investigate the impacts of intelligence and emotional quotient on team resilience capability, the extent to which project team can recover from the impediment and move forward. This is a research-in-progress work. A future empirical test plan has been discussed at the end

    Mechanism of thermal field and electric field in resistive random access memory using the high/low-k side wall structure

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    In the Internet of things (IoT) era, low power consumption memory will be a critical issue for further device development. Among many kinds of next-generation memories, resistive random access memory (RRAM) is considered as having the most potential due to its high performance. To prevent unrecoverable hard break-down of a RRAM device, the RRAM should be collocated with a transistor for external current compliance. With decreasing device cell size, however, the operating voltage of the transistor will become smaller and smaller. Previous study has determined that the forming voltage of RRAM increases when device cell size is reduced, which is a very crucial issue especially when the device is scaled down. We have proposed a high-k sidewall spacer structure in RRAM to solve the dilemma of increasing forming voltages for device cell scaling down. Based on the COMSOL-simulated electrical field distributions in the high-k RRAM. In addition, thermal conductivity of sidewall spacer influenced resistive switching behavior. Suitable thermal conductivity of sidewall materials can enhance resistive switching behavior. Please click Additional Files below to see the full abstract
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