Investigation of Solder Joint Encapsulant Materials for Defect Mitigation

As Cisco’s next-generation products continue to push the trends of higher signal speeds and increased functional density, the need for advanced PCB structures, such as Via-in-Pad Plated Over (VIPPO) and backdrill, and high-speed memory is becoming more mainstream across product platforms.  Furthermore, as these high-speed memory technologies are being driven by consumer applications, the form factor and interconnect pitches continue to shrink to meet the demands of the mobile device market.  The use of these advanced PCB structures, like VIPPO and VIPPO with backdrill, within the BGA footprints, particularly for the fine pitch patterns, have been found to result in BGA solder separation defects at the bulk solder to IMC interface upon a 2nd reflow, e.g. during top-side reflow for bottom-side components or during rework of an adjacent BGA.1  In some cases, this solder separation failure mode has also been identified with buried vias under the BGA pad or even without the presence of VIPPO or any vias under the BGA pad. 2.3 Additionally, these small memory components have been experiencing high occurrences of head-in-pillow (HIP) defects even though the overall package warpage over the reflow profile is &lt; ~3mils.&#x0D; This paper will therefore focus on the mitigation of these solder joint defects resulting from SMT assembly with the use of solder joint encapsulant materials to provide enhanced adhesion strength for the solder joints.  Leveraging existing test vehicles that are known to induce the aforementioned solder joint defects, 2 different solder joint encapsulant or epoxy flux materials are evaluated in terms of the application process, assembly integrity and compatibility with Cisco’s production solder paste materials and SMT processes.</jats:p

Impact of Isothermal Aging and Testing Temperature on Large Flip-Chip BGA Interconnect Mechanical Shock Performance

The stability of solder interconnects in a mechanical shock environment is crucial for large body size flip-chip ball grid array (FCBGA) electronic packages. Additionally, the junction temperature increases with higher electric power condition, which brings the component into an elevated temperature environment, thus introducing another consideration factor for mechanical stability of interconnection joints. Since most of the shock performance data available were produced at room temperature, the effect of elevated temperature is of interest to ensure the reliability of the device in a mechanical shock environment. To achieve a stablea interconnect pound in a dynamic shock environment, the interconnections must tolerate mechanical strain, which is induced by the shock wave input and reaches the particular component interconnect joint. In this study, large body size (52.5 x 52.5 mm(2)) FCBGA components assembled on 2.4-mm-thick boards were tested with various isothermal pre-conditions and testing conditions. With a heating element embedded in the test board, a test temperature range from room temperature to 100A degrees C was established. The effects of elevated temperature on mechanical shock performance were investigated. Failure and degradation mechanisms are identified and discussed based on the microstructure evolution and grain structure transformations