Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process

The measurement of layer-to-layer feature overlay will, in the foreseeable future, continue to be a critical metrological requirement for the semiconductor industry. Meeting the image placement metrology demands of accuracy, precision, and measurement speed favors the use of electrical test structures. In this paper, a two-dimensional, modified voltage-dividing potentiometer is applied to a short-loop VLSI process to measure image placement. The contributions of feature placement on the reticle and overlay on the wafer to the overall measurement are analyzed and separated. Additional sources of uncertainty are identified, and methods developed to monitor and reduce them are described