High Linearity Down-Conversion CMOS Mixers

This paper gives a quantitative analysis of the main mechanisms setting fundamental limits to the linearity performances of CMOS direct down-conversion mixers. An advanced low voltage solution is proposed for 3G cell-phones in a 90 nm CMOS technology that achieves: 3nV/radicHz average input referred noise in the band from 10 kHz to 1.92 MHz, a flicker noise corner of 300 kHz, 9 dBm IIP3 and 75 dBm minimum IIP2 while drawing 5.4 mA from a 1.2 V supply

A 260-MHz RF Bandwidth Mixer-First Receiver with Third-Order Current-Mode Filtering TIA

A mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for the 5G lower frequency band (below 6 GHz) is presented. The filtering trans-impedance amplifier immediately following the mixer is based on a regulated cascode, instead of a conventional shunt-feedback architecture. Thanks to a positive-feedback capacitance multiplication, third-order low-pass filtering in the current domain is performed. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show alternate channel IIP3 and P1dB of +22 dBm and +3 dBm, respectively. RX NF is 5.5 dB while power consumption is 21.6 mW (signal path) and 7.8-mW/GHz (LO) with 1.8/1.2-V supply

Multimode Reconfigurable Wireless Terminals: a First Step Toward Software Defined Radio

Multimedia applications create the need for multi-mode handsets that support many standards with different frequency, bandwidth, modulation etc. Sharing and/or switching blocks in these handsets are used to extend battery life and/or reduce cost. Furthermore adaptive circuits that can reconfigure themselves within the handover time will enable seamless interoperability over several standards with a single receiver/transmitter. This paper presents RF and analog baseband circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. They can trade power consumption for performance on the fly, depending on the standard and the required quality of service. Experimental measurements in a 0.13 mum CMOS technology are presented and discussed

A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA

A highly linear Trans-Impedance Amplifier (TIA) for 5G New Radio mobile communication receivers is presented. The TIA has a cut-off frequency programmable from 500 MHz up to 1.5 GHz. The TIA is based on a Feed-Forward compensated amplifier. To ensure stability while achieving high bandwidth and low power, an inductor is used inside the feed-forward stage. A test chip has been realized in 28 nm CMOS technology. The TIA achieves an In-band O1P3 of 32.9 dBm and the output integrated noise from 20 MHz to 1.5 GHz is lower than 300 mu V-rms with a power dissipation of 17 mW