Combining TCAD and Monte Carlo methods to simulate CMOS pixel sensors with a small collection electrode using the Allpix2^{2} framework

Combining electrostatic field simulations with Monte Carlo methods enables realistic modeling of the detector response for novel monolithic silicon detectors with strongly non-linear electric fields. Both the precise field description and the inclusion of Landau fluctuations and production of secondary particles in the sensor are crucial ingredients for the understanding and reproduction of detector characteristics. In this paper, a CMOS pixel sensor with small collection electrode design, implemented in a high-resistivity epitaxial layer, is simulated by integrating a detailed electric field model from finite element TCAD into a Monte Carlo based simulation with the framework. The simulation results are compared to data recorded in test-beam measurements and very good agreement is found for various quantities such as cluster size, spatial resolution and efficiency. Furthermore, the observables are studied as a function of the intra-pixel incidence position to enable a detailed comparison with the detector behavior observed in data. The validation of such simulations is fundamental for modeling the detector response and for predicting the performance of future prototype designs. Moreover, visualization plots extracted from the charge carrier drift model of the framework can aid in understanding the charge propagation behavior in different regions of the sensor

Performance evaluation of thin active-edge planar sensors for the CLIC vertex detector

Thin planar silicon sensors with a pitch of 55μm, active edge and various guard-ring layouts are investigated,using two-dimensional finite-element T-CAD simulations. The simulation results have been compared toexperimental data, and an overall good agreement is observed. It is demonstrated that the 50μm thick active-edge planar silicon sensors with floating guard-ring or without guard-ring can be operated fully efficiently upto the physical edge of the sensor. The simulation findings are used to identify suitable sensor designs forapplication in the high-precision vertex detector of the future CLIC linear e$^{+}$e$^{-}$ collider

Time resolution studies of Timepix3 assemblies with thin silicon pixel sensors

Timepix3 is a multi-purpose readout ASIC for hybrid pixel detectors. It can measure time and amplitude simultaneously by employing time-of-arrival (ToA) and time-over-threshold (ToT) techniques. Both methods are systematically affected by timewalk. In this paper, a method for pixel-by-pixel calibration of the time response is presented. Assemblies of Timepix3 ASICs bump-bonded to thin planar silicon pixel sensors with thicknesses of 50 μ m, 100 μ m and 150 μ m are calibrated and characterised in particle beams. For minimum ionising particles, time resolutions down to 0.72 ± 0.04 ns are achieved

Does Perceptual Belongingness Affect Lightness Constancy?

Scientists have shown that two equal grey patches may differ in lightness when belonging to different reflecting surfaces. We extend this investigation to the constancy domain. In a CRT simulation of a bipartite field of illumination, we manipulated the arrangement of twelve patches: six squares and six diamonds. Patches of the same shape could be placed: (i) all within the same illumination field; or (ii) forming a row across the illumination fields. Furthermore, we manipulated proximity between the innermost patches and the illumination edge. The patches could be (i) touching (forming an X-junction); or (ii) not touching (not forming an X-junction). Observers were asked to perform a lightness match between two additional patches, one illuminated and the other in shadow. We found better lightness constancy when the patches of the same shape formed a row across the fields, with no effect of X-junctions

Design and characterisation of the CLICTD pixelated monolithic sensor chip

A novel monolithic pixelated sensor and readout chip, the CLIC Tracker Detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the Compact Linear Collider (CLIC), and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of 16×128 elongated channels, each measuring 300×30 μm2. Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit Time-of-Arrival (with 10 ns time bins) and 5-bit Time-over-Threshold measurement is performed on the combined digital output of the 8 sub-pixels in every channel. The chip has been fabricated in two process variants and characterised in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e‾ and a noise of about 14 e‾ RMS. The design aspects and characterisation results of the CLICTD chip are presented

MALTA monolithic pixel sensors in TowerJazz 180 nm technology

Depleted Monolithic Active Pixel Sensors are of highest interest at the HL-LHC and beyond for the replacement of the Pixel trackers in the outermost layers of experiments where the requirement on total area and cost effectiveness is much bigger. They aim to provide high granularity and low material budget over large surfaces with ease of integration. Our research focuses on MALTA, a radiation hard DMAPS with small collection electrode designed in TowerJazz 180 nm CMOS imaging technology and asynchronous read-out. Latest prototypes are radiation hard up to 2 × 1015 1 MeV neq/cm2 with a time resolution better than 2 ns

Testbeam results of the Picosecond Avalanche Detector proof-of-concept prototype

The proof-of-concept prototype of the Picosecond Avalanche Detector, a multi-PN junction monolithic silicon detector with continuous gain layer deep in the sensor depleted region, was tested with a beam of 180 GeV pions at the CERN SPS. The prototype features low noise and fast SiGe BiCMOS frontend electronics and hexagonal pixels with 100 μm pitch. At a sensor bias voltage of 125 V, the detector provides full efficiency and average time resolution of 30, 25 and 17 ps in the overall pixel area for a power consumption of 0.4, 0.9 and 2.7 W/cm2, respectively. In this first prototype the time resolution depends significantly on the distance from the center of the pixel, varying at the highest power consumption measured between 13 ps at the center of the pixel and 25 ps in the inter-pixel region

Picosecond Avalanche Detector — working principle and gain measurement with a proof-of-concept prototype

The Picosecond Avalanche Detector is a multi-junction silicon pixel detector based on a (NP)drift(NP)gain structure, devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamp capability. It uses a continuous junction deep inside the sensor volume to amplify the primary charge produced by ionizing radiation in a thin absorption layer. The signal is then induced by the secondary charges moving inside a thicker drift region. A proof-of-concept monolithic prototype, consisting of a matrix of hexagonal pixels with 100 μm pitch, has been produced using the 130 nm SiGe BiCMOS process by IHP microelectronics. Measurements on probe station and with a 55Fe X-ray source show that the prototype is functional and displays avalanche gain up to a maximum electron gain of 23. A study of the avalanche characteristics, corroborated by TCAD simulations, indicates that space-charge effects due to the large primary charge produced by the conversion of X-rays from the ^55Fe source limits the effective gain

20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer

A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 {\mu}m thick epilayer of 350 {\Omega}cm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.Comment: 11 pages, 11 figure