"CMAD", a Full Custom ASIC, for the Upgrade of COMPASS RICH-1

An 8 channel, full-custom ASIC prototype, named ”CMAD”, designed for the readout of the RICH-I detector system of the COMPASS experiment at CERN is presented. The task of the chip is amplifying the signals coming from fast multi-anode photomultipliers and comparing them against a threshold adjustable on-chip on a channel by channel basis. CMAD, developed using a 350nm commercial CMOS technology, occupies an area of 4.7x3.2mm2 and consumes 26mW/Ch power from a 3.3 V single source

Front end electronics for pixel detector of the PANDA MVD

ToPix 2.0 is a prototype in a CMOS 0.13 ¹m technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 ¹W/cell). In an area of 100¹m£100¹m each cell incorporates the analog and digital electronics necessary to amplify the detector signal and to digitize the time and charge information. The ASIC includes 320 pixel readout cells organized in four columns and a simplified version of the end of column readout

A low-noise CMOS front-end for TOF-PET

An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required (approximate to 100 ps). A CMOS 0.13 mu m technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 mu m. Waveform sampling and time-over-threshold (ToT) techniques are under study and the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a photodetector with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier (approximate to 5 Omega) allows 1.8 ns of peaking time, at the cost of 10 mW of power consumption

Beam test results of the irradiated Silicon Drift Detector for ALICE

The Silicon Drift Detectors will equip two of the six cylindrical layers of high precision position sensitive detectors in the ITS of the ALICE experiment at LHC. In this paper we report the beam test results of a SDD irradiated with 1 GeV electrons. The aim of this test was to verify the radiation tolerance of the device under an electron fluence equivalent to twice particle fluence expected during 10 years of ALICE operation.Comment: 6 pages,6 figures, to appear in the proceedings of International Workshop In high Multiplicity Environments (TIME'05), 3-7 October 2005, Zurich,Switzerlan

CARIOCA: a fast binary front-end implemented in 0.25μ0.25\mu CMOS using a Novel current-mode technique for the LHCb muon detector

The CARIOCA front-end is an amplifier discriminator chip, using 0.25mm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10W. Measurements showed a peaking time of 14ns and noise of 450e- at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC remains almost unchanged up to a detector capacitance of 120pF

A Cylindrical GEM Inner Tracker for the BESIII experiment at IHEP

The Beijing Electron Spectrometer III (BESIII) is a multipurpose detector that collects data provided by the collision in the Beijing Electron Positron Collider II (BEPCII), hosted at the Institute of High Energy Physics of Beijing. Since the beginning of its operation, BESIII has collected the world largest sample of J/{\psi} and {\psi}(2s). Due to the increase of the luminosity up to its nominal value of 10^33 cm-2 s-1 and aging effect, the MDC decreases its efficiency in the first layers up to 35% with respect to the value in 2014. Since BESIII has to take data up to 2022 with the chance to continue up to 2027, the Italian collaboration proposed to replace the inner part of the MDC with three independent layers of Cylindrical triple-GEM (CGEM). The CGEM-IT project will deploy several new features and innovation with respect the other current GEM based detector: the {\mu}TPC and analog readout, with time and charge measurements will allow to reach the 130 {\mu}m spatial resolution in 1 T magnetic field requested by the BESIII collaboration. In this proceeding, an update of the status of the project will be presented, with a particular focus on the results with planar and cylindrical prototypes with test beams data. These results are beyond the state of the art for GEM technology in magnetic field

A low-noise CMOS front-end for TOF-PET

An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required (approximate to 100 ps). A CMOS 0.13 mu m technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 mu m. Waveform sampling and time-over-threshold (ToT) techniques are under study and the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a photodetector with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier (approximate to 5 Omega) allows 1.8 ns of peaking time, at the cost of 10 mW of power consumption

A low-noise CMOS front-end for TOF-PET

An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required (approximate to 100 ps). A CMOS 0.13 mu m technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 mu m. Waveform sampling and time-over-threshold (ToT) techniques are under study and the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a photodetector with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier (approximate to 5 Omega) allows 1.8 ns of peaking time, at the cost of 10 mW of power consumption

A low-noise CMOS front-end for TOF-PET

An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required (approximate to 100 ps). A CMOS 0.13 mu m technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 mu m. Waveform sampling and time-over-threshold (ToT) techniques are under study and the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a photodetector with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier (approximate to 5 Omega) allows 1.8 ns of peaking time, at the cost of 10 mW of power consumption

The Silicon Drift Detector readout scheme for the Inner Tracking System of the ALICE Experiment

Presentation at Quark Matter '99, Torino, Italy, 10-15 May 1999The Silicon Drift Detectors (SDDs) provide, through the measurement of the drift time of the charge deposited by the particle which crosses the detector, information on the impact point and on the energy deposition. The foreseen readout scheme is based on a single chip implementation of an integrated circuit that includes low-noise amplification, fast analog strorage and analog to digital conversion, thus avoiding the problems related to the analog signal transmission. A multi-event buffer that reduces the transmission bandwidth and a data compression/zero suppression unit complete the architecture.Abstract:In this paper, the system components design is described, together with the results of the first prototypes