Association of BMI, lipid-lowering medication, and age with prevalence of type 2 diabetes in adults with heterozygous familial hypercholesterolaemia: a worldwide cross-sectional study

Background: Statins are the cornerstone treatment for patients with heterozygous familial hypercholesterolaemia but research suggests it could increase the risk of type 2 diabetes in the general population. A low prevalence of type 2 diabetes was reported in some familial hypercholesterolaemia cohorts, raising the question of whether these patients are protected against type 2 diabetes. Obesity is a well known risk factor for the development of type 2 diabetes. We aimed to investigate the associations of known key determinants of type 2 diabetes with its prevalence in people with heterozygous familial hypercholesterolaemia. Methods: This worldwide cross-sectional study used individual-level data from the EAS FHSC registry and included adults older than 18 years with a clinical or genetic diagnosis of heterozygous familial hypercholesterolaemia who had data available on age, BMI, and diabetes status. Those with known or suspected homozygous familial hypercholesterolaemia and type 1 diabetes were excluded. The main outcome was prevalence of type 2 diabetes overall and by WHO region, and in relation to obesity (BMI ≥30·0 kg/m2) and lipid-lowering medication as predictors. The study population was divided into 12 risk categories based on age (tertiles), obesity, and receiving statins, and the risk of type 2 diabetes was investigated using logistic regression. Findings: Among 46 683 adults with individual-level data in the FHSC registry, 24 784 with heterozygous familial hypercholesterolaemia were included in the analysis from 44 countries. 19 818 (80%) had a genetically confirmed diagnosis of heterozygous familial hypercholesterolaemia. Type 2 diabetes prevalence in the total population was 5·7% (1415 of 24 784), with 4·1% (817 of 19 818) in the genetically diagnosed cohort. Higher prevalence of type 2 diabetes was observed in the Eastern Mediterranean (58 [29·9%] of 194), South-East Asia and Western Pacific (214 [12·0%] of 1785), and the Americas (166 [8·5%] of 1955) than in Europe (excluding the Netherlands; 527 [8·0%] of 6579). Advancing age, a higher BMI category (obesity and overweight), and use of lipid-lowering medication were associated with a higher risk of type 2 diabetes, independent of sex and LDL cholesterol. Among the 12 risk categories, the probability of developing type 2 diabetes was higher in people in the highest risk category (aged 55–98 years, with obesity, and receiving statins; OR 74·42 [95% CI 47·04–117·73]) than in those in the lowest risk category (aged 18–38 years, without obesity, and not receiving statins). Those who did not have obesity, even if they were in the upper age tertile and receiving statins, had lower risk of type 2 diabetes (OR 24·42 [15·57–38·31]). The corresponding results in the genetically diagnosed cohort were OR 65·04 (40·67–104·02) for those with obesity in the highest risk category and OR 20·07 (12·73–31·65) for those without obesity. Interpretation: Adults with heterozygous familial hypercholesterolaemia in most WHO regions have a higher type 2 diabetes prevalence than in Europe. Obesity markedly increases the risk of diabetes associated with age and use of statins in these patients. Our results suggest that heterozygous familial hypercholesterolaemia does not protect against type 2 diabetes, hence managing obesity is essential to reduce type 2 diabetes in this patient population. Funding: Pfizer, Amgen, MSD, Sanofi-Aventis, Daiichi-Sankyo, and Regeneron

Comprehensive investigation of gate oxide short in fin FETs

Manufacturing complexities due to FinFET's three-dimensional structure and reduced critical dimensions have caused new challenges in achieving reliable device testing. Gate oxide short (GOS) is one of the defects that requires a thorough investigation due to its complexity in 3D transistors and its significant impact on circuit reliability. In this paper, we present a comprehensive study on the transistor defect characteristics as we introduce pinholes in the gate oxide of rectangular fin and trapezoidal fin shape structures. The pinholes are represented by small cuboid cuts of various sizes located along the fin height and channel length. Our analysis is performed with the aid of Synopsys' Sentaurus TCAD tools. The results presented in this paper can lead to the development of more realistic analytical GOS defect model for circuit level simulation

Gate Oxide Short Defect Model in FinFETs

FinFET technology is one of the most promising candidates in replacing planar MOSFET beyond the 22 nm technology node. However, the complexity of FinFET manufacturing process has caused challenges in reliable device testing. Gate oxide short (GOS) is one of the dominant defects that has significant impact on circuit reliability. In this paper, we present a GOS defect model for FinFETs by introducing the defect as a pinhole in the gate oxide of a triangular fin shape structure. The pinholes are represented by small cuboid cuts of various sizes on the fin top and sidewalls along the channel. The 3D Sentaurus TCAD simulation results in the development of an analytical GOS defect model that can be used in circuit-level fault modeling, which leads to generating more realistic test patterns

Efficient Realization of BCD Multipliers Using FPGAs

In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results