Time-mode Circuits For Analog Computation

We introduce time-mode circuits, a set of basic circuit building blocks for analog computation using a temporal step function representation for the inputs and outputs. These novel time-mode circuits are low power, provide good noise performance and offer improved dynamic range. The design, IC implementation and detailed theoretical signal-to-noise ratio (SNR) analysis of a prototype time-mode circuit-a weighted average computation circuit-are discussed. This new way of computation is studied with respect to existing conventional voltage-mode and current-mode circuits. Two possible applications of these time mode circuits are presented: an edge detection circuit for 16 pixels and a 3-tap FIR filter that provides an SNR of 64 dB. © 2008 John Wiley & Sons, Ltd

Technology And Signal Processing For Brain-machine Interfaces

Brain-machine interfaces (BMIs) aid disabled humans. BMI systems face challenges such as interfacing with neural tissue, selecting the most appropriate control signals, acquiring data and decoding patient intent in implantable or wearable computers. They must be able to adapt to different variety of behavioral states. Today\u27s hybrid BMI systems consume less power and are made to chronically extract control commands from the nervous system. In terms of signal processing approaches, one challenge for BMI data analysis is learning how to handle large multi-input multi-output systems with signal representations that span continuous and discrete time. BMI systems also need sufficient information on spatio-temporal representation made by assemblies of neurons. BMIs success is dependent on the ability to first extract control features from neural activity related to goal-directed behavior

FRAMES: A SIMPLE CHARACTERIZATION OF PERMUTATIONS REALIZED BY FREQUENTLY USED NETWORKS

Rearrangeable multistage interconnection networks such as the Benes network realize any permutation, yet their routing algorithms are not cost-effective. On the other hand, non-rearrangeable networks can have inexpensive routing algorithms, but no simple technique exists to characterix all the permutations realized on these netwarks. This paper introduces the concept of frame and shows how iit can be used to characterize all the permutations realized on various multistage inteirconnection networks. They include any subnetwork of the Benes network, the class of networks that are topologically equivalent to the baseline network, and cascaded baseline and shuffle-exchange networks. The question of how the addition of a stage to any of these networks affects the type of permutations realized by the network is precisely answered. Also, of interest from a theoretical standpoint, a new simple proof is provided for the rearrangeability of the Benes network

A case study in synchronous parallel discrete event simulation

This paper considers the suitability of SPED, a synchronous parallel discrete event simulator, for the study of message passing networks. The simulation algorithm is described, and its potential performance is assessed showing that, under some simplifying assumptions, SPED might offer speedups directly proportional to the number of processors used in the simulation. An implementation of SPED in a distributed memory parallel system is used to study a model of an interconnection network for a multicomputer. Experiments show that SPED performs nearly as expected, as long as the event density imposed on the LPs is above a certain threshold. If this is not the case, the overhead due to synchronization plus communication dominates the execution time, and the achieved speedups are not as good. Some ways to improve the performance of SPED are proposed: a method to reduce the number of messages interchanged during the simulation, and a new algorithm for synchronous PDES, called PTD-NB (Parallel Time Driven- No Barriers), which reduces the synchronization overhead by removing barrier operations and can be easily implemented in multicomputer systems without support for global synchronization operations

Dist a distribution independent parallel programs for matrix multiplication

This report considers the problem of writing data distribution independent (DDI) programs in order to eliminate or reduce initial data redistribution overheads for distributed memory parallel computers. The functionality and execution time of DDI programs are independent of initial data distributions. First, modular mappings, which can be used to derive many equally optimal ant1 functionally equivalent programs, are briefly reviewed. Relations between modular mappings and input data distributions are then established. These relations are the basis of a systematic approach to the derivation of DDI programs which is illustrated for matrix-matrix multiplication(c = a x b). Conditions on data distributions that correspond to an optimal modular mapping are: (1) the first row of the inverse of distribution pattern matrix of army \u27a\u27 should be equal to the second row of the inverse of distribution pattern matrix of array \u27b\u27) (2) the second row of the inverse of distribution pattern matrix of array \u27a\u27 should be linearly independent of the first row of the inverse of distribution pattern matrix of array \u27b\u27, and (3) each distribution pattern matrix of arrays \u27a\u27, \u27b\u27, and \u27c\u27 should have at [east one zero entry, respectively. It is shown that only twelve programs suffice to accomplish redistribution-free execution for the many input data distributions that satisfy the above conditions. When DDI matrix multiplication programs are used in an algorithm with multiple matrix products, half of data redistributions otherwise required can be eliminated