The Modern FPGA as Discriminator, TDC and ADC

Recent generations of Field Programmable Gate Arrays (FPGAs) have become indispensible tools for complex state machine control and signal processing, and now routinely incorporate CPU cores to allow execution of user software code. At the same time, their exceptional performance permits low-power implementation of functionality previously the exclusive domain of dedicated analog electronics. Specific examples presented here use FPGAs as discriminator, time-to-digital (TDC) and analog-to-digital converter (ADC). All three cases are examples of instrumentation for current or future astroparticle experiments.Comment: 7 pages, v3 minor JINST editorial correction

A Monolithic Time Stretcher for Precision Time Recording

Identifying light mesons which contain only up/down quarks (pions) from those containing a strange quark (kaons) over the typical meter length scales of a particle physics detector requires instrumentation capable of measuring flight times with a resolution on the order of 20ps. In the last few years a large number of inexpensive, multi-channel Time-to-Digital Converter (TDC) chips have become available. These devices typically have timing resolution performance in the hundreds of ps regime. A technique is presented that is a monolithic version of ``time stretcher'' solution adopted for the Belle Time-Of-Flight system to address this gap between resolution need and intrinsic multi-hit TDC performance.Comment: 9 pages, 15 figures, minor corrections made, to appear as JINST_008

The first version Buffered Large Analog Bandwidth (BLAB1) ASIC for high luminosity collider and extensive radio neutrino detectors

Future detectors for high luminosity particle identification and ultra high energy neutrino observation would benefit from a digitizer capable of recording sensor elements with high analog bandwidth and large record depth, in a cost-effective, compact and low-power way. A first version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has been very successful and forms the basis of a generation of new, large-scale radio neutrino detectors, its limited sampling depth is a major drawback. A prototype has been designed and fabricated with 65k deep sampling at multi-GSa/s operation. We present test results and directions for future evolution of this sampling technique.Comment: 15 pages, 26 figures; revised, accepted for publication in NIM

High Voltage CMOS Control Interface for Astronomy - Grade Charged Coupled Devices

The Pan-STARRS telescope consists of an array of smaller mirrors viewed by a Gigapixel arrays of CCDs. These focal planes employ Orthogonal Transfer CCDs (OTCCDs) to allow on-chip image stabilization. Each OTCCD has advanced logic features that are controlled externally. A CMOS Interface Device for High Voltage has been developed to provide the appropiate voltage signal levels from a readout and control system designated STARGRASP. OTCCD chip output levels range from -3.3V to 16.7V, with two different output drive strenghts required depending on load capacitance (50pF and 1000pF), with 24mA of drive and a rise time on the order of 100ns. Additional testing ADC structures have been included in this chip to evaluate future functional additions for a next version of the chip.Comment: 13 pages, 17 gigure

Design, Activation, and Operation of the J2-X Subscale Simulator (JSS)

The purpose of this paper is to give a detailed description of the design, activation, and operation of the J2-X Subscale Simulator (JSS) installed in Cell 1 of the E3 test facility at Stennis Space Center, MS (SSC). The primary purpose of the JSS is to simulate the installation of the J2-X engine in the A3 Subscale Rocket Altitude Test Facility at SSC. The JSS is designed to give aerodynamically and thermodynamically similar plume properties as the J2-X engine currently under development for use as the upper stage engine on the ARES I and ARES V spacecraft. The JSS is a scale pressure fed, LOX/GH fueled rocket that is geometrically similar to the J2-X from the throat to the nozzle exit plane (NEP) and is operated at the same oxidizer to fuel ratios and chamber pressures. This paper describes the heritage hardware used as the basis of the JSS design, the newly designed rocket hardware, igniter systems used, and the activation and operation of the JSS

Description and Operation of the A3 Subscale Facility

The purpose of this paper is to give an overview of the general design and operation of the A3 Subscale test facility. The goal is to provide the reader with a general understanding of what the major facility systems are, where they are located, and how they are used to meet the objectives supporting the design of the A3 altitude rocket test facility. This paper also provides the reader with the background information prior to reading the subsequent papers detailing the design and test results of the various systems described herein

TARGET: A Digitizing And Trigger ASIC For The Cherenkov Telescope Array

The future ground-based gamma-ray observatory Cherenkov Telescope Array (CTA) will feature multiple types of imaging atmospheric Cherenkov telescopes, each with thousands of pixels. To be affordable, camera concepts for these telescopes have to feature low cost per channel and at the same time meet the requirements for CTA in order to achieve the desired scientific goals. We present the concept of the TeV Array Readout Electronics with GSa/s sampling and Event Trigger (TARGET) Application Specific Circuit (ASIC), envisaged to be used in the cameras of various CTA telescopes, e.g. the Gamma-ray Cherenkov Telescope (GCT), a proposed 2-Mirror Small-Sized Telescope, and the Schwarzschild-Couder Telescope (SCT), a proposed Medium-Sized Telescope. In the latest version of this readout concept the sampling and trigger parts are split into dedicated ASICs, TARGET C and T5TEA, both providing 16 parallel input channels. TARGET C features a tunable sampling rate (usually 1 GSa/s), a 16k sample deep buffer for each channel and on-demand digitization and transmission of waveforms with typical spans of ~100 ns. The trigger ASIC, T5TEA, provides 4 low voltage differential signal (LVDS) trigger outputs and can generate a pedestal voltage independently for each channel. Trigger signals are generated by T5TEA based on the analog sum of the input in four independent groups of four adjacent channels and compared to a threshold set by the user. Thus, T5TEA generates four LVDS trigger outputs, as well as 16 pedestal voltages fed to TARGET C independently for each channel. We show preliminary results of the characterization and testing of TARGET C and T5TEA.Comment: 6 pages, 8 figures, Proceedings of the 6th International Symposium on High-Energy Gamma-Ray Astronomy (Gamma2016

A Scintillating Fiber Hodoscope for a Bremstrahlung Luminosity Monitor at an Electron−-Positron Collider

The performance of a scintillating fiber (2mm diameter) position sensitive detector ($4.8 \times 4.8$ cm$^2$ active area) for the single bremstrahlung luminosity monitor at the VEPP-2M electron-positron collider in Novosibirsk, Russia is described. Custom electronics is triggered by coincident hits in the X and Y planes of 24 fibers each, and reduces 64 PMT signals to a 10 bit (X,Y) address. Hits are accumulated (10 kHz) in memory and display (few Hz) the VEPP-2M collision vertex. Fitting the strongly peaked distribution ( $\sim$ 3-4 mm at 1.6m from the collision vertex of VEPP-2M ) to the expected QED angular distribution yields a background in agreement with an independent determination of the VEPP-2M luminosity.Comment: LaTeX with REVTeX style and options: multicol,aps. 8 pages, postscript figures separate from text. Accepted in Review of Scientific Instruments (~ Aug 1996