Concurrent error detection in Reed-Solomon encoders and decoders

Reed-Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, self-checking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in GF(2(m)). These properties are related to the parity of the binary representation of the elements of the Galois Field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented

Optimized implementation of RNS FIR filters based on FPGAs

In this paper optimized Residue Number System (RNS) arithmetic blocks to better exploit some of the architectural characteristics of the last generation FPGAs are presented. The implementation of modulo m adders, modulo m constant and general multipliers, input and output converters are presented. These architectures are based on moduli sets chosen in order to optimally use the 6-input Look-Up Tables (LUTs) available in the Complex Logic Blocks (CLBs) of the new generation FPGAs. Experiments based on the implementation of Finite Impulse Response (FIR) filters characterized by different number of taps and wordlengths shows that the use of RNS together with suitable moduli sets optimally fits the 6-input LUTs in the last generation FPGAs architectures. © Springer Science+Business Media, LLC 2010

Partial reconfiguration in the implementation of autonomous radio receivers for space

n space mission there are different scenarios where autonomous radio systems are very useful. In this paper we consider one of such scenarios, related to the communication infrastructure for the planet exploration. The basic idea is to obtain significant advantages in au- tonomous radio receiver implementation by using FPGA dynamic partial reconfiguration. Implementing the most significant part of the radio, we will show as this techniques can be used and what are the advantages we can obtain. In particular, by using this design methodology system complexity and power consumption is reduced improving the overall system reliability (mainly, in relation to possible SEU induced by ions in the configuration memory)