Quantization of Prior Probabilities for Hypothesis Testing

Bayesian hypothesis testing is investigated when the prior probabilities of the hypotheses, taken as a random vector, are quantized. Nearest neighbor and centroid conditions are derived using mean Bayes risk error as a distortion measure for quantization. A high-resolution approximation to the distortion-rate function is also obtained. Human decision making in segregated populations is studied assuming Bayesian hypothesis testing with quantized priors

Performance of LDPC Codes Under Faulty Iterative Decoding

Departing from traditional communication theory where decoding algorithms are assumed to perform without error, a system where noise perturbs both computational devices and communication channels is considered here. This paper studies limits in processing noisy signals with noisy circuits by investigating the effect of noise on standard iterative decoders for low-density parity-check codes. Concentration of decoding performance around its average is shown to hold when noise is introduced into message-passing and local computation. Density evolution equations for simple faulty iterative decoders are derived. In one model, computing nonlinear estimation thresholds shows that performance degrades smoothly as decoder noise increases, but arbitrarily small probability of error is not achievable. Probability of error may be driven to zero in another system model; the decoding threshold again decreases smoothly with decoder noise. As an application of the methods developed, an achievability result for reliable memory systems constructed from unreliable components is provided.Comment: Revised in May 2010 in response to reviewer comment

Multitone PSK Modulation Design for Simultaneous Wireless Information and Power Transfer

Far-field wireless power transfer, based on radio frequency (RF) waves, came into the picture to fulfill the power need of large Internet of Things (IoT) networks, the backbone of the 5G and beyond era. However, RF communication signals carry both information as well as energy. Therefore, recently, simultaneous wireless information and power transfer (SWIPT) has attracted much attention in order to wirelessly charge these IoT devices. In this paper, we propose a novel N -tone multitone phase shift keying (PSK) modulation scheme, taking advantage of the non-linearity of integrated receiver rectifier architecture. The main advantage of the proposed modulation scheme is the reduction in ripple voltage, introduced by the symbol transmission through phases. Achievable power conversion efficiency (PCE) and bit error rate (BER) at the output are considered to measure the efficacy of the proposed modulation scheme. Simulation results are verified by the measurements over the designed rectifier circuitry. The effect of symbol phase range, modulation order, and the number of tones are analyzed. In the future, this transmission scheme can be utilized to satisfy the data and power requirements of low-power Internet of Things sensor networks

On the Fast Generation of Long-period Pseudorandom Number Sequences

Abstract-Monte Carlo simulations and other scientific applications that depend on random numbers are increasingly implemented in parallel configurations in programmable hardware. High-quality pseudo-random number generators (PRNGs), such as the Mersenne Twister, are based on binary linear recurrence equations. They have extremely long periods (more than 2 1024 numbers generated before the entire sequence repeats) and wellproven statistical properties. Many software implementations of such 'long-period' PRNGs exist, but hardware implementations are rare. We develop optimized, resource-efficient parallel architectures for long-period PRNGs that generate multiple independent streams by exploiting the underlying algorithm as well as hardware-specific architectural features. We demonstrate the utility of the framework through parallelized implementations of three types of PRNGs on a fieldprogrammable gate array (FPGA). The area/throughput performance is impressive: for example, compared clock-for-clock with a previous FPGA implementation, a "two-parallelized" 32-bit Mersenne Twister uses 41% fewer resources. It can also scale to 350 MHz for a throughput of 22.4 Gbps, which is 5.5x faster than the previous implementation and 7.1x faster than a dedicated software implementation. The quality of generated random numbers is verified with standard statistical test batteries. To complete testing, we present a real-world application study by coupling our parallel hardware RNGs to the Ziggurat algorithm for generating normal random variables. The availability of fast long-period random number generators accelerates hardware-based scientific simulations and allows them to scale to greater complexities