Hadronic B Decays to Charmless VT Final States

Charmless hadronic decays of B mesons to a vector meson (V) and a tensor meson (T) are analyzed in the frameworks of both flavor SU(3) symmetry and generalized factorization. We also make comments on B decays to two tensor mesons in the final states. Certain ways to test validity of the generalized factorization are proposed, using $B \to VT$ decays. We calculate the branching ratios and CP asymmetries using the full effective Hamiltonian including all the penguin operators and the form factors obtained in the non-relativistic quark model of Isgur, Scora, Grinstein and Wise.Comment: 27 pages, no figures, LaTe

Shape matching and clustering in design

Generalising knowledge and matching patterns is a basic human trait in re-using past experiences. We often cluster (group) knowledge of similar attributes as a process of learning and or aid to manage the complexity and re-use of experiential knowledge [1, 2]. In conceptual design, an ill-defined shape may be recognised as more than one type. Resulting in shapes possibly being classified differently when different criteria are applied. This paper outlines the work being carried out to develop a new technique for shape clustering. It highlights the current methods for analysing shapes found in computer aided sketching systems, before a method is proposed that addresses shape clustering and pattern matching. Clustering for vague geometric models and multiple viewpoint support are explored

Quantum random number generation for 1.25 GHz quantum key distribution systems

Security proofs of quantum key distribution (QKD) systems usually assume that the users have access to source of perfect randomness. State-of-the-art QKD systems run at frequencies in the GHz range, requiring a sustained GHz rate of generation and acquisition of quantum random numbers. In this paper we demonstrate such a high speed random number generator. The entropy source is based on amplified spontaneous emission from an erbium-doped fibre, which is directly acquired using a standard small form-factor pluggable (SFP) module. The module connects to the Field Programmable Gate Array (FPGA) of a QKD system. A real-time randomness extractor is implemented in the FPGA and achieves a sustained rate of 1.25 Gbps of provably random bits.Comment: 6 pages, 8 figure

Fast decimal floating-point division

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literatureHooman Nikmehr, Braden Phillips and Cheng-Chew Li

Critical currents for vortex defect motion in superconducting arrays

We study numerically the motion of vortices in two-dimensional arrays of resistively shunted Josephson junctions. An extra vortex is created in the ground states by introducing novel boundary conditions and made mobile by applying external currents. We then measure critical currents and the corresponding pinning energy barriers to vortex motion, which in the unfrustrated case agree well with previous theoretical and experimental findings. In the fully frustrated case our results also give good agreement with experimental ones, in sharp contrast with the existing theoretical prediction. A physical explanation is provided in relation with the vortex motion observed in simulations.Comment: To appear in Physical Review

Quantum Tomographic Cryptography with a Semiconductor Single Photon Source

In this paper we analyze the security of the so-called quantum tomographic cryptography with the source producing entangled photons via an experimental scheme proposed in Phys. Rev. Lett. 92, 37903 (2004). We determine the range of the experimental parameters for which the protocol is secure against the most general incoherent attacks

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.Singapore-MIT Alliance (SMA