GTRACE-RS: Efficient Graph Sequence Mining using Reverse Search

The mining of frequent subgraphs from labeled graph data has been studied extensively. Furthermore, much attention has recently been paid to frequent pattern mining from graph sequences. A method, called GTRACE, has been proposed to mine frequent patterns from graph sequences under the assumption that changes in graphs are gradual. Although GTRACE mines the frequent patterns efficiently, it still needs substantial computation time to mine the patterns from graph sequences containing large graphs and long sequences. In this paper, we propose a new version of GTRACE that enables efficient mining of frequent patterns based on the principle of a reverse search. The underlying concept of the reverse search is a general scheme for designing efficient algorithms for hard enumeration problems. Our performance study shows that the proposed method is efficient and scalable for mining both long and large graph sequence patterns and is several orders of magnitude faster than the original GTRACE

Effects of interface electric field on the magnetoresistance in spin device

An extension of the standard spin diffusion theory is presented by introducing a density-gradient (DG) term that is suitable for describing interface quantum tunneling phenomena. The magnetoresistance (MR) ratio is modified by the DG term through an interface electric field. We have also carried out spin injection and detection measurements using four-terminal Si devices. The local measurement shows that the MR ratio changes depending on the current direction. We show that the change of the MR ratio depending on the current direction comes from the DG term regarding the asymmetry of the two interface electronic structures.Comment: 5 pages, 3 figure

Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin FPGA owing to the nonvolatile memory function of spin MOSFET.Comment: 3 pages, 7 figure

Reactivity of TEMPO anion as a nucleophile and its applications for selective transformations of haloalkanes or acyl halides to aldehydes

Sodium 2,2,6,6-tetramethylpiperidine-N-oxide (TEMPO&#8722;Na+), generated by reduction of TEMPO· with sodium naphthalenide in THF, reacted with alkyl halides or acyl halides to produce O-alkylated or acylated TEMPOs, which were in turn oxidized with mCPBA or reduced with DIBAL-H to afford the corresponding aldehydes, thus accomplishing a new protocol for the halides-carbonyls conversion.</p