31 research outputs found

    A new VME trigger processor for the NA57 experiment

    Get PDF
    The ALICE experiment will use a trigger concept requiring independent deadtimes for each sub-detector system, and with detector-specific past-future protection. These features are implemented in a new VME-based trigger processor for the NA57 experiment. Monitoring and diagnostic features of the new trigger processor are also described.List of Figures Figure 1:ALICE trigger logic diagram. Figure 2:Layout of the NA57 experiment. Figure 3:Schematic layout of NA57 VME central trigger processor. Figure 4:Example of a trigger definition script. </A

    Determination of the number of wounded nucleons in Pb+Pb collisions at 158 A GeV/c

    Get PDF
    The charged particle multiplicity distributions measured by two experiments, WA97 and NA57, in Pb+Pb collisions at 158 A GeV/c have been analyzed in the framework of the wounded nucleon model (WNM). We obtain a good description of the data within the centrality range of our samples. This allows us to make use of the measured multiplicities to estimate the number of wounded nucleons of the collision

    ATLAS detector and physics performance: Technical Design Report, 1

    Get PDF

    The ALICE DATE: the benefits of using hardware and software industry standards in a real-time environment

    No full text
    In 1996, the ALICE DAQ group was confronted to future demands which Abstract:were exceeding the capabilities of the system used up to then. After Abstract:some review of the market, we decided to integrate a newAbstract:data-acquisition system using several different new components.Abstract:In six months, a system has been developed using new VME boards,Abstract:a new version of Unix, a new switching netowrk and new I/O interfaces. Abstract:Despite the very short deadline, the integration of this system Abstract:has been extremely effective and has been ready on time and usedAbstract:during the tests of fall '97. One of the reasons of this success Abstract:was the use of industrially supported hardware and software standards.Abstract:The general architecture of the system will be described togetherAbstract:with the different input/output devices used in the system Abstract:(Fast Ethernet, PCI, FDDI, Fast Wide SCSI) and the corresponding Abstract:performances. The software environment, tools and languages (Unix, Abstract:Tcl/Tk, Java) used for this system will also be presented
    corecore