Multiple Functionality in Nanotube Transistors

Calculations of quantum transport in a carbon nanotube transistor show that such a device offers unique functionality. It can operate as a ballistic field-effect transistor, with excellent characteristics even when scaled to 10 nm dimensions. At larger gate voltages, channel inversion leads to resonant tunneling through an electrostatically defined nanoscale quantum dot. Thus the transistor becomes a gated resonant tunelling device, with negative differential resistance at a tunable threshold. For the dimensions considered here, the device operates in the Coulomb blockade regime, even at room temperature.Comment: To appear in Phys. Rev. Let

Study of conduction in vertical and lateral nanostructures

It is predicted that Quantum devices would be used to develop future high-speed computers. The demonstration of quantum phenomenon in metal and semiconductor devices has been limited to temperatures of 4.2K or lower due to the minimum achievable feature sizes of conventional fabrication techniques. A vertical sidewall gating technique has been developed to study and demonstrate lateral confinement effects in quantum heterostructures. Room temperature pinch-off of the resonant peak in single well resonant devices with minimum widths in the sub-micron regime and an even gating in both positive and negative biasing regimes are presented. The first demonstration of pinch-off of multiple well resonant structures including observation of one-dimensional quantization and sub-band mixing at 77K is reported. A self-assembled structure of nanometer size single crystal metal metal clusters with organic linking between nearest neighbour clusters has been developed at Purdue with possible applications in future single electronic circuits. Activated temperature dependent conduction has been observed in these linked cluster networks (LCN) and is associated to the charging energy of a single charge (soliton) in the array. Changing the linking molecule between the clusters changes the conduction through the array and is associated to the conduction properties of the organic linking molecule. While room-temperature Coulomb blockade is not observed, means to achieve the same using the LCN structures are discussed

Chemically Stable Semiconductor Surface Layers Using Low-Temperature Grown GaAs

AbstractThe chemical stability of a GaAs layer structure consisting of a thin (10 nm) layer of low-temperature-grown GaAs (LTG:GaAs) on a heavily n-doped GaAs layer, both grown by molecular beam epitaxy, is described. Scanning tunneling spectroscopy and X-ray photoelectron spectroscopy performed after atmospheric exposure indicate that the LTG:GaAs surface layer oxidizes much less rapidly than comparable layers of stoichiometric GaAs. There is also evidence that the terminal oxide thickness is smaller than that of stoichiometric GaAs. The spectroscopy results are used to confirm a model for conduction in low resistance, nonalloyed contacts employing comparable layer structures. The inhibited surface oxidation rate is attributed to the bulk Fermi level pinning and the low minority carrier lifetime in unannealed LTG:GaAs. Device applications including low-resistance cap layers for field-effect transistors are described.</jats:p

Process Control Challenges and Solutions: TEOS, W, and CU CMP

Various options that afford control of the TEOS, W, and Cu/barrier polishes were explored in the building of multilevel dual inlaid structures. Improved tool performance that enables more sophisticated down pressure control with higher resolution backpressure adjustments was employed for the oxide module to control the interlevel capacitances. Planarity at both the global and local levels at the oxide polish affords a good starting point for successive builds without metal pooling. In W CMP, small and controllable oxide erosion and plug recess was obtained with harder polishing pads. In Cu/barrier CMP, the tight overpolish/underpolish margin was maintained by head control and appropriate endpoint algorithms. A six-level build with tight and low sheet resistances and leakages was demonstrated.</jats:p

Nanoelectronic device applications of a chemically stable GaAs structure

We report on nanoelectronic device applications of a nonalloyed contact structure which utilizes a surface layer of low-temperature grown GaAs as a chemically stable surface. In contrast to typical ex situ ohmic contacts formed on n-type semiconductors such as GaAs, this approach can provide uniform contact interfaces which are essentially planar injectors, making them suitable as contacts to shallow devices with overall dimensions below 50 nm. Characterization of the native layers and surfaces coated with self-assembled monolayers of organic molecules provides a picture of the chemical and electronic stability of the layer structures. We have recently developed controlled nanostructures which incorporate metallic nanoclusters, a conjugated organic interface layer, and the chemically stable semiconductor surface layers. These studies indicate that stable nanocontacts (4 nmX4 nm) can be realized with specific contact resistances less than 1 X 10(-6) Ohm cm(2) and maximum current densities (1 X 10(6) A/cm(2)) comparable to those observed in high quality large area contacts. The ability to form stable, low resistance interfaces between metallic nanoclusters and semiconductor device layers using ex situ processing allows chemical self-assembly techniques to be utilized to form interesting nanoscale semiconductor devices. This article will describe the surface and nanocontact characterization results, and will discuss device applications and novel techniques for patterning close-packed arrays of nanocontacts and for imaging the resulting structures. (C) 1999 American Vacuum Society. [S0734-211X(99)05504-3]