Non-linearity reduction technique for delay-locked delay-lines

A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-locked delay-line (DLL) is achieved by performing a statistical test on the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently realizing the technique is described. Simulation results show the feasibility of the technique and the significant reduction of the non-linearity obtained with only four additional shunt capacitor couples per cell