Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model. The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works

Design of matrix, distributive round robin, ping pong and enhanced ping lock arbiter for shared resources systems

Arbiter is one of the main core elements in the network scheduler. The significant goal of this work is to design a high-speed and low execution-time arbiter with lock free and fair arbitration scheme. In this work, four types of arbiters such as matrix arbiter (MA), ping pong arbiter (PPA), distributive round-robin arbiter (DRRA) and enhanced ping lock arbiter (EPLA) are designed and analyzed area, delay, and speed of arbiters. MA is worked in square matrix format and matrix transition is performed for effective routing. The DRRA is designed by using a multiplexer and counter. Hence an, effective scheduling is carried out in DRRA. Binary tree format is used in PPA. The PPA provides low chip size and high speed than existing MA and DRRA. The PPA limits fair arbitration during uniformly distributed active request patterns. To overcome this problem, PPA is improved with some lock systems to create an EPLA. A new ping lock arbiter (PLA) leaf and PLA inter structure is proposed at the gate level to reduce the execution delay, improve the speed and achieve fair arbitration over all other existing arbiters. Resource allocation, execution delay, and speed are analyzed using the Xilinx Integrated Software Environment (ISE) tool