30 research outputs found
Reliability Aware AMS/RF Performance Optimization
Reliability has become an important issue in the continuously CMOS technology scaling down. The exploration of the technology limits using classic performance optimization techniques and leads to the best trade-off for the area, power consumption, and speed. Nevertheless, such key characteristics have been degraded in a context of continuous use and stressful environment. Thus, circuit reliability emerges as a design criterion for AMS/RF performance optimization. Aiming a design for reliability, this chapter presents an overview of CMOS unreliable phenomena. Reliability-aware methodologies for circuit design, simulation, and optimization are reviewed. The authors focus in particular on large and complex systems, providing circuit design insights to achieve a reliability specification from system-level to transistor-level. They highlight the more sensitive building blocks in CT S? modulator and demonstrate how performance is affected by unreliable phenomena. A system-level direct-conversion RF front-end design is described in top-down approach. Electrical simulations are presented with 65 nm CMOS technology. </jats:p
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters
A novel BIST for monitoring aging/temperature by self-triggered scheme to improve the reliability of STT-MRAM
Antibacterial activity of the marine diatom Skeletonema costatum against aquacultural pathogens
Reliability evaluation of circuits designed in multi- and single-stage versions
International audienceNanometer circuits suffer heavily from fabrication, transient and permanent failures. Circuit reliability has to be added to the design space. Probabilistic transfer matrix is an exact method to calculate the reliability of a circuit. Traditionally, logic gates are the basic blocks of this method with a constant reliability for all gates and all possible input vector combination. This paper introduces the importance of considering the transistor arrangement as a pre-processing step and presents an analysis of logic functions designed in single- and multi-stage versions. The results show that single-stage versions present higher reliability when compared to the multi-stage solution. These results confirm the higher robustness induced by more complex arrangements
