Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

Bump bonding is a superior assembly alternative compared to conventional wire bond techniques. It offers a highly reliable connection with greatly reduced parasitic properties. The Flip Chip on Board (FCOB) procedure is an especially attractive packaging method for applications requiring a large number of connections at moderate pitch. This paper reports on the successful demonstration of FCOB assembly based on solder bumps down to 250um pitch using a SUESS MA8 flip chip bonder at Fermilab. The assembly procedure will be described, microscopic cross sections of the connections are shown, and first measurements on the contact resistance are presented.Comment: 4 pages, 8 figure

Readout Concepts for DEPFET Pixel Arrays

Field effect transistors embedded into a depleted silicon bulk (DEPFETs) can be used as the first amplifying element for the detection of small signal charges deposited in the bulk by ionizing particles, X-ray photons or visible light. Very good noise performance at room temperature due to the low capacitance of the collecting electrode has been demonstrated. Regular two dimensional arrangements of DEPFETs can be read out by turning on individual rows and reading currents or voltages in the columns. Such arrangements allow the fast, low power readout of larger arrays with the possibility of random access to selected pixels. In this paper, different readout concepts are discussed as they are required for arrays with incomplete or complete clear and for readout at the source or the drain. Examples of VLSI chips for the steering of the gate and clear rows and for reading out the columns are presented.Comment: 8 pages, 9 figures, submitted to Nucl. Instr. and Methods as proceedings of the 9th European Symposium on Semiconductor Detectors, Elmau, June 23-27, 200

Status of a DEPFET pixel system for the ILC vertex detector

We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated using different radioactive sources in an energy range from 6 to 40keV. In recent test beam experiments using 6GeV electrons, a signal-to-noise ratio of S/N~120 has been achieved with present sensors being 450 micron thick. For improved DEPFET systems using 50 micron thin sensors in future, a signal-to-noise of 40 is expected.Comment: Invited poster at the International Symposium on the Development of Detectors for Particle, AstroParticle and Synchrotron Radiation Experiments, Stanford CA (SNIC06) 6 pages, 12 eps figure

SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm{sup 2} large detector array with 20 {micro}m and 40 {micro}m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well

News, intelligence and 'little lies' : rumours between the Cherokees and the British 1740-1785

Rumour and information are one of the most fundamental ways in which people engage with one another. Rumours can change the way that individuals and groups see each other and the actions that they take. Sociologists and anthropologists have long used rumour as a way to explore the experiences of their subjects. Historians of early America have, in recent years, begun to make use of rumour as a way of examining the, often hidden, world of interactions between American Indians and white Europeans. This thesis will expand upon this work by exploring the changing role of rumour within an intercultural relationship over several decades. This thesis will focus on rumour in the relationship between the Cherokee Nation and the colonists of the British Empire. It will explore the ways that rumour influenced these interactions and the impact of the rapidly changing backcountry environment of the latter eighteenth century, both on rumour and on the wider Cherokee- British relationship. This thesis will argue that rumour shifted in the course of the eighteenth century from being a diplomatic tool which could be used- either to create further panic and confusion or to calm and smooth over problems- to an uncontrollable force which would deepen and exacerbate the divisions between Cherokees and the British. Rumour played an important role in politics and society in the eighteenth century backcountry and its changing function offers a way to better understand the shifting currents of life in early America

Design and technology of DEPFET pixel sensors for linear collider applications

Abstract The performance requirements of vertex detectors for future linear collider experiments is very challenging, especially for the detector's innermost sensor layers. The DEPleted Field Effect Transistor (DEPFET), combining detector and amplifier operation, is capable to meet these requirements. A silicon technology is presented which allows production of large sensor arrays consisting of linear DEPFET detector structures. The envisaged pixel array offers low noise and low power operation. To ensure a high radiation length a thinning technology based on direct wafer bonding is proposed

SPi User Manual V0.1

This document describes the Serial Powering Interface (SPi) ASIC. SPi is a general purpose ASIC prototype designed for use in serial powering of silicon detector instrumentation. This description is written as a user manual to aid application, not as a design description. SPi is a generic custom ASIC, manufactured in 0.25 {mu}m CMOS by TSMC, to interface between a constant current source and silicon detector read-out chips. There is no SEU (single event upset) protection, but most (not all) components are radiation tolerant design. An operating voltage of 1.2 to 2.5 volts and other design features make the IC suitable for a variety of serial powering architectures and ROICs. It should be noted that the device is likely to be a prototype for demonstration rather than a product for inclusion in a detector. The next design(s), SPin, are likely to be designed for a specific application (eg SLHC). The component includes: (1) Seven bi-directional LVDS-like buffers for high data rate links to/from the read-out chips. These are AC coupled (series capacitor) off-chip for DC level conversion; (2) A programmable internal programmable shunt regulator to provide a defined voltage to readout chips when linked in a serial powering chain; (3) A programmable internal shunt regulator control circuit for external transistor control; (4) Shunt current measurement (for internal shunt regulator); (5) A programmable internal shunt regulator current alarm; and (6) Two programmable linear regulators

SPi User Manual V0.1

This document describes the Serial Powering Interface (SPi) ASIC. SPi is a general purpose ASIC prototype designed for use in serial powering of silicon detector instrumentation. This description is written as a user manual to aid application, not as a design description. SPi is a generic custom ASIC, manufactured in 0.25 {mu}m CMOS by TSMC, to interface between a constant current source and silicon detector read-out chips. There is no SEU (single event upset) protection, but most (not all) components are radiation tolerant design. An operating voltage of 1.2 to 2.5 volts and other design features make the IC suitable for a variety of serial powering architectures and ROICs. It should be noted that the device is likely to be a prototype for demonstration rather than a product for inclusion in a detector. The next design(s), SPin, are likely to be designed for a specific application (eg SLHC). The component includes: (1) Seven bi-directional LVDS-like buffers for high data rate links to/from the read-out chips. These are AC coupled (series capacitor) off-chip for DC level conversion; (2) A programmable internal programmable shunt regulator to provide a defined voltage to readout chips when linked in a serial powering chain; (3) A programmable internal shunt regulator control circuit for external transistor control; (4) Shunt current measurement (for internal shunt regulator); (5) A programmable internal shunt regulator current alarm; and (6) Two programmable linear regulators