CORE
CO
nnecting
RE
positories
Services
Services overview
Explore all CORE services
Access to raw data
API
Dataset
FastSync
Content discovery
Recommender
Discovery
OAI identifiers
OAI Resolver
Managing content
Dashboard
Bespoke contracts
Consultancy services
Support us
Support us
Membership
Sponsorship
Research partnership
About
About
About us
Our mission
Team
Blog
FAQs
Contact us
Community governance
Governance
Advisory Board
Board of supporters
Research network
Innovations
Our research
Labs
Filters
2 research outputs found
Architecting the last-level cache for GPUs using STT-MRAM nonvolatile memory
Author
H. Sarbazi-Azad
M. Arjomand
M.H. Samavatian
R. Bashizade
Publication venue
Elsevier
Publication date
01/01/2017
Field of study
Full text link
Crossref
List of Contributors
Author
A. Bhowmick
A. Ganguly
+73 more
A. Jog
A. Lokhmotov
A. Pathania
A. Prakash
A. Yang
A. Yazdanbakhsh
A.C.M.A. de Melo
A.F. Donaldson
B. Jang
B. Wu
C. Das
C.-R. Lee
D. El Baz
D. Lavenier
D. Troendle
D. Tullsen
F. Busato
F. Hesaaraki
F. Khunjush
G. Chapuis
G. Gopalakrishnan
G. Jo
G. Li
G. Pekhimenko
H. Djidjev
H. Esmaeilzadeh
H. Kim
H. Mukka
H. Sarbazi-Azad
H. Sharma
J. Coplin
J. Ketema
J. Kim
J. Lee
J. Li
J. Park
J. Park
J. Tan
J. Wadden
K. Skadron
M. Arjomand
M. Burtscher
M. Gopi
M. Kandemir
M.A. Salazar-Aguilar
M.H. Samavatian
N. Bombieri
N. Chong
N. Mansoor
N. Moreano
N. Vijaykumar
O. Mutlu
P. Li
P. Lotfi-Kamran
P. Zardoshti
R. Andonov
R. Ausavarungnirun
R. Bashizade
R. Nath
S. Ghose
S. Qadeer
S. Ranka
S. Sahni
S.L. Alarcon
T. Mitra
T. Ta
T.C. Mowry
V. Boyer
W. Jung
X. Fu
X. Shen
Y.-C. Chen
Y.-J. Lee
Publication venue
Elsevier
Publication date
01/01/2017
Field of study
Full text link
Crossref
Full text link
