1,573 research outputs found

    Corporate Yield Spreads: Default Risk or Liquidity? New Evidence from the Credit-Default Swap Market

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    We use the information in credit-default swaps to obtain direct measures of the size of the default and nondefault components in corporate spreads. We find that the majority of the corporate spread is due to default risk. This result holds for all rating categories and is robust to the definition of the riskless curve. We also find that the nondefault component is time varying and strongly related to measures of bond-specific illiquidity as well as to macroeconomic measures of bond-market liquidity.

    Acquisition, representation and rule generation for procedural knowledge

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    Current research into the design and continuing development of a system for the acquisition of procedural knowledge, its representation in useful forms, and proposed methods for automated C Language Integrated Production System (CLIPS) rule generation is discussed. The Task Analysis and Rule Generation Tool (TARGET) is intended to permit experts, individually or collectively, to visually describe and refine procedural tasks. The system is designed to represent the acquired knowledge in the form of graphical objects with the capacity for generating production rules in CLIPS. The generated rules can then be integrated into applications such as NASA's Intelligent Computer Aided Training (ICAT) architecture. Also described are proposed methods for use in translating the graphical and intermediate knowledge representations into CLIPS rules

    A general technique for deterministic model-cycle-level debugging

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    Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the model-cycle boundaries if only implementation-cycle-level control and information is provided. A good debugging facility needs to provide: complete control over the functioning of the target design being simulated; fast and easy access to all the significant target design state for both monitoring and modification; and some means of accomplishing deterministic execution when the target design is a multicore processor running a parallel application. Moreover, these features need to be provided in a manner which does not incur substantial resource and performance penalties. In this paper, we present a debugging technique based on the LI-BDN theory. We show how the technique facilitates deterministic model-cycle-level debugging. We used it to build the debugging infrastructure for Arete, which is an FPGA-based cycle-accurate multicore simulator. The resource and performance penalties of our debugging technique are minimal; in Arete the debugging infrastructure has area and performance overheads of 5% and 6%, respectively.IBM Researc

    Wilis: Architectural Modeling of Wireless Systems

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    The performance of a wireless system depends on the wireless channel as well as the algorithms used in the transceiver pipelines. Because physical phenomena affect transceiver pipelines in difficult to predict ways, detailed simulation of the entire transceiver system is needed to evaluate even a single processing block. Further, some protocol validations require simulation of rare events (say, 1 bit error in 109 bits), which means the protocol must simulate for a long enough time for such events to materialize. This requirement coupled with the heavy computation typical of most physical-layer processing, rules out pure software solutions. In this paper we describe WiLIS, an FPGA-based hybrid hardware-software system designed to facilitate the development of wireless protocols. We then use WiLIS to evaluate several microarchitectures for measuring very low bit-error rates (BER). We demonstrate, for the first time, that the recently proposed SoftPHY can be implemented efficiently in hardware

    Dietary beliefs and eating patterns influence metabolic health in type 2 diabetes: A clinic-based study in urban North India

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    Background: Almost 15% of India\u27s urban adult populace now lives with type 2 diabetes. This study aimed to characterize the eating patterns, knowledge, beliefs, and determinants of food choice, and assess associations with the metabolic health among urban Asian Indians with type 2 diabetes. Materials and Methods: A cross-sectional study of 258 individuals (mean age 55.7 ± 10 years; body mass index 27.1 ± 4.8 kg/m 2 ; diabetes duration 10.1 ± 6.5 years) attending two out-patient clinics in New Delhi, India. Food-related information was collected during a semi-structured interview. Clinical, anthropometric, and biochemical data were recorded. Results: Beliefs related to health and diabetes played a role determining food choice and dietary patterns; erroneous views were associated with the poor food choices and greater metabolic perturbations. Average consumption of fruits/vegetables was low. Intakes were positively associated with intentions to manage diabetes; inversely associated with the waist circumference and negatively correlated with one\u27s degree of personal responsibility for food choice. Household saturated fat usage was common. High fat intakes were positively associated with the taste preference, ratings of perceived "health-value;" waist circumference, glycosylated haemoglobin percentage (HbA1c%) and lipids. Conclusions: Strategies to enhance diabetes control among Asian Indians are required and should encourage fruit/vegetable intake, personal accountability, and consider individual beliefs and preferences. Greater emphasis and resources directed to regular dietary and behavioral counseling may assist.

    Verification of microarchitectural refinements in rule-based systems

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    http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5970511&tag=1Microarchitectural refinements are often required to meet performance, area, or timing constraints when designing complex digital systems. While refinements are often straightforward to implement, it is difficult to formally specify the conditions of correctness for those which change cycle-level timing. As a result, in the later stages of design only those changes are considered that do not affect timing and whose verification can be automated using tools for checking FSM equivalence. This excludes an essential class of microarchitectural changes, such as the insertion of a register in a long combinational path to meet timing. A design methodology based on guarded atomic actions, or rules, offers an opportunity to raise the notion of correctness to a more abstract level. In rule-based systems, many useful refinements can be expressed simply by breaking a single rule into smaller rules which execute the original operation in multiple steps. Since the smaller rule executions can be interleaved with other rules, the verification task is to determine that no new behaviors have been introduced. We formalize this notion of correctness and present a tool based on SMT solvers that can automatically prove that a refinement is correct, or provide concrete information as to why it is not correct. With this tool, a larger class of refinements at all stages of the design process can be verified easily. We demonstrate the use of our tool in proving the correctness of the refinement of a processor pipeline from four stages to five.National Science Foundation (U.S.) (NSF (#CCF-0541164)

    Lithotectonic Landslides and Hazards in Parts of Garhwal-Kumaon Himalayas

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    Landslides produce an awesome picture of the hill sides with steep scarred, hollowed and gullied geomorphic features devoid of vegetation particularly between the major thrust zones. A look on the tectono-stratigraphic map of the region with marked major tectonic features like the Main Central Thrust (MCT), North Almora Thrust (NAT) and South Almora Thrust (SAT) indicates that the region is highly prone to landslides and is affected by repeated tectonic and orogenic processes. These factors with the nature of the rocks, climate and the heavy monsoon rains are responsible for sculpturing the region. The mountain features and the valley slopes thus indicate the influence of the activities and the dynamic forces at a particular locality and time. Many times developmental activities have also contributed towards the degradation of the environs due to disturbance of the already stabilized slopes and the angles of repose e.g. along the Rishikesh-Badrinath Road, where a new alignment has been given, sometimes overlapping the old pilgrim route
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