Laboratory and beam-test performance study of a 55 µm pitch iLGAD sensor bonded to a Timepix3 readout chip

This contribution reports on characterisation results of a large-area (2 cm2) small pitch (55 µm) inverse Low-Gain Avalanche Detector (iLGAD), bonded to a Timepix3 readout chip. The ilGAD sensors were produced by Micron Semiconductor Ltd with the goal to obtain good gain uniformity and maximise the fill-factor — an issue present with standard small-pitch LGAD designs. We have conducted detailed performance evaluations using both X-ray calibrations and beam tests. An X-ray fluorescence setup has been used to obtain energy calibration and to identify the optimal operating settings of the new devices, whereas the extensive beam tests allowed for a detailed evaluation of the detector performance. The beam-tests were performed at the CERN SPS North Area H6 beamline, using a 120 GeV/c pion beam. The reference tracking and time-stamping is achieved by a Timepix3-based beam telescope setup. The results show a gain of around 5 with very good uniformity, measured across the whole gain area, as well as a hit time resolution down to 1.3 ns without correcting for the time-walk effects. Furthermore, it is shown that the gain opens the possibility of a good X-ray energy resolution down to 4.5 keV

A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5×1.5 mm including a matrix of 32×32 pixels with a pitch of 15μm . The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42μm2 and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

International audienceThe long term goal of the CERN Experimental Physics Department R&D on monolithic sensorsis the development of sub-100nm CMOS sensors for high energy physics. The first technologyselected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 includedseveral small test chips with sensor and circuit prototypes and transistor test structures. One ofthe main questions to be addressed was how to optimize the sensor in the presence of significantin-pixel circuitry. In this paper this optimization is described as well as the experimental resultsfrom the MLR1 run confirming its effectiveness. A second submission investigating wafer-scalestitching has just been completed. This work has been carried out in strong synergy with the ITS3upgrade of the ALICE experiment

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

The long term goal of the CERN Experimental Physics Department R&D; on monolithic sensorsis the development of sub-100nm CMOS sensors for high energy physics. The first technologyselected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 includedseveral small test chips with sensor and circuit prototypes and transistor test structures. One ofthe main questions to be addressed was how to optimize the sensor in the presence of significantin-pixel circuitry. In this paper this optimization is described as well as the experimental resultsfrom the MLR1 run confirming its effectiveness. A second submission investigating wafer-scalestitching has just been completed. This work has been carried out in strong synergy with the ITS3upgrade of the ALICE experiment