Integrated electronics for a CdTe based PET system

ISBN 978142443962International audienceIn this paper, we present two circuits designed for pulse readout of a semiconductor PET system: a fast low noise low power front-end preamplifier/shaper, and the processing circuit performing time tagging, energy measurement and digital interfacing with the data acquisition system. Considerations on noise, speed and power consumption are discussed. The system level electronics architecture and its optimization according to the detector architecture is presented. Results of the circuits caracteristics are also presented

Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations

International audienceDesign of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of low granularity of these 3D interconnect elements, this methodology becomes less effective for 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIVs) with higher density (around 1.10 8 vias per mm 2 ). In this paper, we describe a methodology to create a unified design environment for 3D sequential technology by merging Process Design Kits (PDKs) of different technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing. As a proof of concept, we designed and taped-out a RISC-V processor with logic on memory architecture using LETI CoolCube 28nm FDSOI on top of ST 28nm FDSOI technology

Charge-based Sense Demonstration in 1T-1C HZO FeRAM Arrays to Overcome C BL -induced Bank Size Limitations

International audienceIn this paper, we propose a new charge-based sensing scheme for read operation in ferroelectric random access memory (FeRAM) arrays. Experimental demonstration on 16kbit up to 256kbit Hf x Zr 1-x O 2 (HZO)-based one transistor - one capacitor (1T-1C) FeRAM arrays reveals that this capacitive trans-impedance amplifier (CTIA)-based sensing has several key advantages over conventional voltage-based sense amplifiers (SA). The major benefits of this innovation are i) a median memory window (MW) as large as 1000mV which is ii) quasi-independent of array size, overcoming the well-known MW closure with bitline capacitance (C BL ) increase observed in FeRAM arrays with conventional voltage-based sense. This new sensing scheme is expected to be of most importance for large HZO FeRAM arrays integrated at advanced nodes, as it enables to increase memory bank size

New perspectives for multicore architectures using advanced technologies

International audienceImpact of advanced technologies on the design and structure of multicore architectures is presented in this paper. More specifically, the power consumption and design complexity walls are examined leading to a “conquer-and-divide” strategy based on multicore partitioning and specialization. We then show how 3D stacking, Monolithic 3D integration and BEOL NVM can be associated to build new, simplified and power- efficient multicore

Convolution neural network inference using frequency modulation in computational phase-change memory

International audienceIn [1] we reported for the first time a frequency modulation method to control the conductance level in PCM cells. This increases the programming reliability of PCM, which is crucial for neuromorphic applications. We provided a physical picture and a physics-based analytical model to link the programming frequency to a target conductance. In this new report, we are the first to successfully demonstrate frequency modulation on 16kbit PCM array in a real case scenario. We first convert synaptic weights in target conductivities, next we translate them into modulation frequencies and transfer values to the PCM array. Eventually, we evaluate the accuracy of a test CNN (Convolutional Neural Network) based on pre-programmed PCM values for recognizing handwritten digits from the MNIST database. We evaluate different redundancies schemes and show up to 90% accuracy and high reliability. We complement our model after careful characterization of the distribution in the programming error (|G target -G pcm |) and show that we can fully predict the inference accuracy. PCM drift characterization shows good data stability over 24 hours at room temperature. Eventually we propose a block schematic of a FSM (Finite State Machine) to implement the frequency modulation on-chip, showing the benefit of such an approach as ease of design