Thermal-Safe Test Scheduling for Core-Based System-on-a-Chip Integrated Circuits

Overheating has been acknowledged as a major problem during the testing of complex system-on-chip (SOC) integrated circuits. Several power-constrained test scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the non-uniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test scheduling approach that is able to produce short test schedules and guarantee thermal-safety at the same time. Two thermal-safe test scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test scheduling algorithm may not be feasible. Based on a low-complexity test session thermal cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm

The sheep conceptus modulates proteome profiles in caruncular endometrium during early pregnancy

This project was funded by NHS Grampian R&D project number RG05/019Peer reviewedPostprin

Cost Model-Driven Test Resource Partitioning for SoCs

The increasing complexity of modern SoCs and quality expectations are making the cost of test represent an significant fraction of the manufacturing cost. The main factors contributing to the cost of test are the required number of tester pins, the test application time, the tester memory requirements and the area overhead required by the test resources. These factors contribute with different weights, depending on the cost model of each product. Several methods have been proposed to optimize each of these factors, however none of them allows an objective function derived from the actual cost model of each product. In this paper, we propose a cost model-driven test resource allocation and scheduling method that minimizes the cost of test

Phase transitions in the Shastry-Sutherland lattice

Two recently developed theoretical approaches are applied to the Shastry-Sutherland lattice, varying the ratio $J'/J$ between the couplings on the square lattice and on the oblique bonds. A self-consistent perturbation, starting from either Ising or plaquette bond singlets, supports the existence of an intermediate phase between the dimer phase and the Ising phase. This existence is confirmed by the results of a renormalized excitonic method. This method, which satisfactorily reproduces the singlet triplet gap in the dimer phase, confirms the existence of a gapped phase in the interval $0.66<J'/J<0.86$Comment: Submited for publication in Phys. Rev.

Report No. 31: The Role of Social Protection as an Economic Stabiliser: Lessons from the Current Crisis

Report based on a study conducted for the European Parliament, Bonn 2010 (188 pages)