926 research outputs found

    Piecewise uniform switched vector quantization of the memoryless two-dimensional Laplace source

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    A simple and complete asymptotical analysis of an optimal piecewise uniform quantization of two-dimensional memoryless Laplacian source with the respect to distortion (D) i.e. the mean-square error (MSE) is presented. Piecewise uniform quantization consists of L different uniform vector quan-tizers. Uniform quantizer optimality conditions and all main equations for optimal number of output points and levels for each partition are presented (using rectangular cells). The optimal granular distortion (i) for each partition in a closed form is derived. Switched quantization is used in order to give higher quality by increasing signal-to-quantization noise ratio (SQNR) in a wide range of signal volumes (variances) or to decrease necessary sample rate

    Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

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    The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180180 nm HV-CMOS process and contains a matrix of 128×128128\times128 square pixels with 2525 μ\mum pitch. First prototypes have been produced with a standard resistivity of 20\sim20 Ω\Omegacm for the substrate and tested in standalone mode. The results show a rise time of 20\sim20 ns, charge gain of 190190 mV/ke^{-} and 40\sim40 e^{-} RMS noise for a power consumption of 4.84.8 μ\muW/pixel. The main design aspects, as well as standalone measurement results, are presented.Comment: 13 pages, 13 figures, 2 tables. Work carried out in the framework of the CLICdp collaboratio

    On Majorization for Matrices

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    In this paper, we give several results for majorized matrices by using continuous convex function and Green function. We obtain mean value theorems for majorized matrices and also give corresponding Cauchy means, as well as prove that these means are monotonic. We prove positive semi-definiteness of matrices generated by differences deduced from majorized matrices which implies exponential convexity and log-convexity of these differences and also obtain Lypunov's and Dresher's type inequalities for these differences

    Prototyping of an HV-CMOS demonstrator for the High Luminosity-LHC upgrade

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    HV-CMOS sensors can offer important advantages in terms of material budget, granularity and cost for large area tracking systems in high energy physics experiments. This article presents the design and simulated results of an HV-CMOS pixel demonstrator for the High Luminosity-LHC. The pixel demonstrator has been designed in the 0.35 μm HV-CMOS process from ams AG and submitted for fabrication through an engineering run. To improve the response of the sensor, different wafers with moderate to high substrate resistivities are used to fabricate the design. The prototype consists of four large analog and standalone matrices with several pixel flavours, which are all compatible for readout with the FE-I4 ASIC. Details about the matrices and the pixel flavours are provided in this article

    Status of a DEPFET pixel system for the ILC vertex detector

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    We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated using different radioactive sources in an energy range from 6 to 40keV. In recent test beam experiments using 6GeV electrons, a signal-to-noise ratio of S/N~120 has been achieved with present sensors being 450 micron thick. For improved DEPFET systems using 50 micron thin sensors in future, a signal-to-noise of 40 is expected.Comment: Invited poster at the International Symposium on the Development of Detectors for Particle, AstroParticle and Synchrotron Radiation Experiments, Stanford CA (SNIC06) 6 pages, 12 eps figure

    A high time resolution and high dynamic range ASIC for the micro-vertex detector in the PANDA experiment

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    A monolithic pixel sensor test chip for the PANDA micro-vertex detector has been implemented in a 180 nm HVCMOS technology on a high resistivity substrate. The sensor should have very high time resolution (1 ns sigma) and high dynamic range (up to 1000). The pixel electronics contains a charge sensitive amplifier, a feedback circuit and two comparators. One comparator receivesn the fast signal and enables accurate time measurement. The other comparator receives the low pass filtered signal and is used for precise amplitude measurement. This publication presents several novel features of the PANDA ASIC, its characterization and several measurement results

    Status of HVCMOS developments for ATLAS

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    This paper describes the status of the developments made by ATLAS HVCMOS and HVMAPS collaborations. We have proposed two HVCMOS sensor concepts for ATLAS pixels—the capacitive coupled pixel detector (CCPD) and the monolithic detector. The sensors have been implemented in three semiconductor processes AMS H18, AMS H35 and LFoundry LFA15. Efficiency of 99.7% after neutron irradiation to 1015 neq/cm2W has been measured with the small area CCPD prototype in AMS H18 technology. About 84% of the particles are detected with a time resolution better than 25 ns. The sensor was implemented on a low resistivity substrate. The large area demonstrator sensor in AMS H35 process has been designed, produced and successfully tested. The sensor has been produced on different high resistivity substrates ranging from 80 Ωcm to more than 1 kΩ. Monolithic- and hybrid readout are both possible. In August 2016, six different monolithic pixel matrices for ATLAS with a total area of 1 cm2 have been submitted in LFoundry LFA15 process. The matrices implement column drain and triggered readout as well as waveform sampling capability on pixel level. Design details will be presented

    Infrastructure for Detector Research and Development towards the International Linear Collider

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    The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

    Radiation-hard active pixel sensors for HL-LHC detector upgrades based on HV-CMOS technology

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    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation at room temperature. A traditional readout chip is still needed to receive and organize the data from the active sensor and to handle high-level functionality such as trigger management. HV-CMOS has been designed to be compatible with both pixel and strip readout. In this paper an overview of HV2FEI4, a HV-CMOS prototype in 180 nm AMS technology, will be given. Preliminary results after neutron and X-ray irradiation are shown

    Belle II Technical Design Report

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    The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un
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