The TASTE Toolset: turning human designed heterogeneous systems into computer built homogeneous software.

The TASTE tool-set results from spin-off studies of the ASSERT project, which started in 2004 with the objective to propose innovative and pragmatic solutions to develop real-time software. One of the primary targets was satellite flight software, but it appeared quickly that their characteristics were shared among various embedded systems. The solutions that we developed now comprise a process and several tools ; the development process is based on the idea that real-time, embedded systems are heterogeneous by nature and that a unique UML-like language was not helping neither their construction, nor their validation. Rather than inventing yet another "ultimate" language, TASTE makes the link between existing and mature technologies such as Simulink, SDL, ASN.1, C, Ada, and generates complete, homogeneous software-based systems that one can straightforwardly download and execute on a physical target. Our current prototype is moving toward a marketed product, and sequel studies are already in place to support, among others, FPGA systems

Note de synthèse sur le cycle évolutif des sarcosporidies affectant les animaux domestiques

Après un bref rappel de la variété des espèces affectées, nous rappelons la nature coccidienne des sarcosporidies. Nous exposons le cycle évolutif de ces parasites tel qu'il a pu être établi expérimentalement à ce jour. Nous mentionnons également les caractères particuliers de ces sporozoaires, qui les différencient de Toxoplasma gondii et de Hammondia hammond

Tetrix depressa (Brisout, 1848) une espèce d’orthoptère nouvelle pour la Vendée (Orthoptera, Tetrigidae)

The writer describes the discovery of Depressed Groundhopper, Tetrix depressa (Brisout, 1848) in a disused quarry in Benet. It's a new species of Groundhopper in Vendée (France)

Premier inventaire des Orthoptères de l’île d’Yeu (Vendée)

A first inventory of Yeu island’s Orthoptera (Vendée, France) allow us to list 23 species and 4 species of the allied orders Mantodea, Phasmodea and Dermaptera. A faunistic study was established on each species and a discussion gives an evaluation of the imprint of human activity on insular Orthoptera’s communities

Confrontation de composites textile-mortier (TRC) à renfort carbone ou acier pour le renforcement d'éléments de maçonnerie.

International audience Une forte demande émerge concernant les techniques de renforcement de structures maçonnées existantes. En réponse, le renforcement par moulage au contact de composites à renfort textile et matrice cimentaire communément nommés textile-mortier (textile reinforced concrete, TRC) s'est développé au cours de ces cinq dernières années. Un essai permettant de caractériser le comportement en traction directe du TRC ainsi que le comportement de l'ancrage TRC/maçonnerie a été développé. Des TRC innovants renforcés par tissus d'acier inoxydable ont été testés et comparés à des TRC renforcés par grilles de carbone. Cette campagne d'essai a montré que le renforcement de structures maçonnées par moulage au contact de TRC renforcés par tissus d'acier inoxydable est technologiquement faisable. Les résultats opposent un comportement à l'arrachement ductile des TRC acier à un comportement fragile des TRC carbone. Cette différence de comportement est principalement liée à la différence de mode de rupture : les TRC carbone montrent un mode de rupture par arrachement (pull-out) entre le textile et la matrice tandis que les TRC acier rompent par un délaminage progressif de l'ancrage. </div

La sarcosporidiose chez le buffle africain (Syncerus caffer)

Après quelques généralités sur la sarcosporidiose, une description des kystes sarcosporidiens trouvés chez le buffle africain (S. caffer) et quelques hypothèses sur le cycle évolutif sont donnée

Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system allows to improve its efficiency and its flexibility thanks to their programmability. To exploit these devices, the designer has to identify the functionalities that have to be executed on them and provide their implementation by means of Hardware Description Languages. Generating these descriptions for a software developer could be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). State of the art tools implementing such methodologies have not been designed for the integration with aerospace systems design flows, so significant adaptations could be required to the designer for integrating the hardware implementations with the rest of the design solution. In this paper the integration of a High Level Synthesis design flow in the TASTE framework (http://taste.tuxfamily.org) is presented. TASTE is a set of freely available tools for the development of real time embedded systems developed by the European Space Agency together with a set of its industrial partners. This framework allows to integrate specifications described in different languages (e.g., C, ADA, Simulink, SDL) by means of formal languages (AADL and ASN.1) and to early verify the correctness of the produced solutions. TASTE has been extended with Bambu (http://panda.dei.polimi.it), a tool for the High Level Synthesis developed at Politecnico di Milano. In this way the TASTE users have the possibility to specify which functionalities, provided by means of high level languages such C, have to be implemented in hardware on the FPGA without having to directly provide the hardware implementations. Thanks to the integration of the High Level Synthesis tool indeed, the framework is able not only to produce the hardware implementations, but also to integrate them in the rest of the aerospace system by automatically generating the whole architecture to be implemented on the FPGA. This architecture contains not only the implementation of the hardware accelerators, but also of the components required to transfer the data from and to the rest of the system and to correctly manage their size and endianness. The application of the extended framework to a real case study shows its effective usability

Multidimensional Ultrasound Doppler Signal Analysis for Fetal Activity Monitoring

International audienceFetal activity parameters such as movements, heart rate and the related parameters are essential indicators of fetal wellbeing, and no device provides simultaneous access to and sufficient estimation of all of these parameters to evaluate fetal health. This work was aimed at collecting these parameters to automatically separate healthy from compromised fetuses. To achieve this goal, we first developed a multi-sensor-multi-gate Doppler system. Then we recorded multidimensional Doppler signals and estimated the fetal activity parameters via dedicated signal processing techniques. Finally, we combined these parameters into four sets of parameters (or four hyper-parameters) to determine the set of parameters that is able to separate healthy from other fetuses. To validate our system, a data set consisting of two groups of fetal signals (normal and compromised) was established and provided by physicians. From the estimated parameters, an instantaneous Manning-like score, referred to as the ultrasonic score, was calculated and was used together with movements, heart rate and the associated parameters in a classification process employing the support vector machine method. We investigated the influence of the sets of parameters and evaluated the performance of the support vector machine using the computation of sensibility, specificity, percentage of support vectors and total classification error. The sensitivity of the four sets ranged from 79% to 100%. Specificity was 100% for all sets. The total classification error ranged from 0% to 20%. The percentage of support vectors ranged from 33% to 49%. Overall, the best results were obtained with the set of parameters consisting of fetal movement, short-term variability, long-term variability, deceleration and ultrasound score. The sensitivity, specificity, percentage of support vectors and total classification error of this set were respectively 100%, 100%, 35% and 0%. This indicated our ability to separate the data into two sets (normal fetuses and pathologic fetuses), and the results highlight the excellent match with the clinical classification performed by the physicians. This work indicates the feasibility of detecting compromised fetuses and also represents an interesting method of close fetal monitoring during the entire pregnancy

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system improves its efficiency and its flexibility thanks to their programmability, but increases the design complexity. The design flows indeed have to be composed of several steps to fill the gap between the starting solution, which is usually a reference sequential implementation, and the final heterogeneous solution which includes custom hardware accelerators. Among these steps, there are the analysis of the application to identify the functionalities that gain advantages in execution on hardware and the generation of their implementations by means of Hardware Description Languages. Generating these descriptions for a software developer can be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). With respect to other embedded systems scenarios, the aerospace systems introduce further constraints that have to be taken into account during the design of these heterogeneous systems. In this type of systems explicit data transfers to and from FPGAs are preferred to the adoption of a shared memory architecture. The first approach indeed potentially improves the predictability of the produced solutions, but the sizes of all the data transferred to and from any devices must be known at design time. Identifying the sizes in presence of complex C applications which use pointers can be a not so easy task. In this paper, a semi-automatic design flow based on the integration of an aerospace design flow, an application analysis technique, and High Level Synthesis methodologies is presented. The initial reference application is analyzed to identify which are the sizes of the data exchanged among the different components of the application. Next, starting from the high level specification and from the results of this analysis, High Level Synthesis techniques are applied to automatically produce the hardware accelerators