Rapid codesign of a soft vector processor and its compiler

Despite a decade of activity in the development of soft vector processors for FPGAs, high-level language support remains thin. We attribute this problem to a design method in which the high-level vector programming interface is only really considered once the processor architecture has been perfected, by which point the designer may be committed to the timeconsuming development of a complicated compiler. In this paper, we present the codesign of a soft vector processor and a lightweight compiler, which together lift the level of abstraction for the programmer while allowing a rapid compiler implementation phase.We demonstrate the effectiveness of our approach on a range of applications from digital signal processing, neuroscience, and machine learning.This work is sponsored by EPSRC grant EP/G015783/1.This is the accepted manuscript version. The final version is available at http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6927425&tag=1. © IEEE 201

Programming Model to Develop Supercomputer Combinatorial Solvers

© 2017 IEEE. Novel architectures for massively parallel machines offer better scalability and the prospect of achieving linear speedup for sizable problems in many domains. The development of suitable programming models and accompanying software tools for these architectures remains one of the biggest challenges towards exploiting their full potential. We present a multi-layer software abstraction model to develop combinatorial solvers on massively-parallel machines with regular topologies. The model enables different challenges in the design and optimization of combinatorial solvers to be tackled independently (separation of concerns) while permitting problem-specific tuning and cross-layer optimization. In specific, the model decouples the issues of inter-node communication, n ode-level scheduling, problem mapping, mesh-level load balancing and expressing problem logic. We present an implementation of the model and use it to profile a Boolean satisfiability solver on simulated massively-parallel machines with different scales and topologies

A consistency checker for memory subsystem traces

Verifying the memory subsystem in a modern shared-memory multiprocessor is a big challenge. Optimized implementations are highly sophisticated, yet must provide subtle consistency and liveness guarantees for the correct execution of concurrent programs. We present a tool that supports efficient specification-based testing of the memory subsystem against a range of formally specified consistency models. Our tool operates directly on the memory subsystem interface, promoting a compositional approach to system-on-chip verification, and can be used to search for simple failure cases – assisting rapid debug. It has recently been incorporated into the development flows of two open-source implementations – Berkeley’s Rocket Chip (RISCV) and Cambridge’s BERI (MIPS) – where it has uncovered a number of serious bugs.This work was supported by DARPA/AFRL contracts FA8750-10-C-0237 (CTSRD) and FA8750-11-C-0249 (MRC2), and EPSRC grant EP/K008528/1 (REMS).This is the author accepted manuscript

Fluctuations, dissipation and the dynamical Casimir effect

Vacuum fluctuations provide a fundamental source of dissipation for systems coupled to quantum fields by radiation pressure. In the dynamical Casimir effect, accelerating neutral bodies in free space give rise to the emission of real photons while experiencing a damping force which plays the role of a radiation reaction force. Analog models where non-stationary conditions for the electromagnetic field simulate the presence of moving plates are currently under experimental investigation. A dissipative force might also appear in the case of uniform relative motion between two bodies, thus leading to a new kind of friction mechanism without mechanical contact. In this paper, we review recent advances on the dynamical Casimir and non-contact friction effects, highlighting their common physical origin.Comment: 39 pages, 4 figures. Review paper to appear in Lecture Notes in Physics, Volume on Casimir Physics, edited by Diego Dalvit, Peter Milonni, David Roberts, and Felipe da Rosa. Minor changes, a reference adde

General hardware multicasting for fine-grained message-passing architectures

Manycore architectures are increasingly favouring message-passing or partitioned global address spaces (PGAS) over cache coherency for reasons of power efficiency and scalability. However, in the absence of cache coherency, there can be a lack of hardware support for one-to-many communication patterns, which are prevalent in some application domains. To address this, we present new hardware primitives for multicast communication in rack-scale manycore systems. These primitives guarantee delivery to both colocated and distributed destinations, and can capture large unstructured communication patterns precisely. As a result, reliable multicast transfers among any number of software tasks, connected in any topology, can be fully offloaded to hardware. We implement the new primitives in a research platform consisting of 50K RISC-V threads distributed over 48 FPGAs, and demonstrate significant performance benefits on a range of applications expressed using a high-level vertex-centric programming model

Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process

The root causes of many security vulnerabilities include a pernicious combination of two problems, often regarded as inescapable aspects of computing. First, the protection mechanisms provided by the mainstream processor architecture and C/C++ language abstractions, dating back to the 1970s and before, provide only coarse-grain virtual-memory-based protection. Second, mainstream system engineering relies almost exclusively on test-and-debug methods, with (at best) prose specifications. These methods have historically sufficed commercially for much of the computer industry, but they fail to prevent large numbers of exploitable bugs, and the security problems that this causes are becoming ever more acute. In this paper we show how more rigorous engineering methods can be applied to the development of a new security-enhanced processor architecture, with its accompanying hardware implementation and software stack. We use formal models of the complete instruction-set architecture (ISA) at the heart of the design and engineering process, both in lightweight ways that support and improve normal engineering practice -- as documentation, in emulators used as a test oracle for hardware and for running software, and for test generation -- and for formal verification. We formalise key intended security properties of the design, and establish that these hold with mechanised proof. This is for the same complete ISA models (complete enough to boot operating systems), without idealisation. We do this for CHERI, an architecture with \emph{hardware capabilities} that supports fine-grained memory protection and scalable secure compartmentalisation, while offering a smooth adoption path for existing software. CHERI is a maturing research architecture, developed since 2010, with work now underway on an Arm industrial prototype to explore its possible adoption in mass-market commercial processors. The rigorous engineering work described here has been an integral part of its development to date, enabling more rapid and confident experimentation, and boosting confidence in the design.This work was supported by EPSRC programme grant EP/K008528/1 (REMS: Rigorous Engineering for Mainstream Systems). This work was supported by a Gates studentship (Nienhuis). This project has received funding from the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement 789108, ELVER). This work was supported by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contracts FA8750-10-C-0237 (CTSRD), HR0011-18-C-0016 (ECATS), and FA8650-18-C-7809 (CIFV)

Experimental infection in calves with a specific subtype of verocytotoxin-producing Escherichia coli O157:H7 of bovine origin

<p>Abstract</p> <p>Background</p> <p>In Sweden, a particular subtype of verocytotoxin-producing <it>Escherichia coli </it>(VTEC) O157:H7, originally defined as being of phage type 4, and carrying two <it>vtx</it>₂genes, has been found to cause the majority of reported human infections during the past 15 years, including both sporadic cases and outbreaks. One plausible explanation for this could be that this particular subtype is better adapted to colonise cattle, and thereby may be excreted in greater concentrations and for longer periods than other VTEC O157:H7 subtypes.</p> <p>Methods</p> <p>In an experimental study, 4 calves were inoculated with 10⁹colony forming units (cfu) of strain CCUG 53931, representative of the subtype VTEC O157:H7 (PT4;<it>vtx</it>₂;<it>vtx</it>_2c). Two un-inoculated calves were co-housed with the inoculated calves. Initially, the VTEC O157:H7 strain had been isolated from a dairy herd with naturally occurring infection and the farm had previously also been linked to human infection with the same strain. Faecal samples were collected over up to a 2-month period and analysed for VTEC O157 by immuno-magnetic separation (IMS), and IMS positive samples were further analysed by direct plating to elucidate the shedding pattern. Samples were also collected from the pharynx.</p> <p>Results</p> <p>All inoculated calves proved culture-positive in faeces within 24 hours after inoculation and the un-inoculated calves similarly on days 1 and 3 post-inoculation. One calf was persistently culture-positive for 43 days; in the remainder, the VTEC O157:H7 count in faeces decreased over the first 2 weeks. All pharyngeal samples were culture-negative for VTEC O157:H7.</p> <p>Conclusion</p> <p>This study contributes with information concerning the dynamics of a specific subtype of VTEC O157:H7 colonisation in dairy calves. This subtype, VTEC O157:H7 (PT4;<it>vtx</it>_2;<it>vtx</it>_2c), is frequently isolated from Swedish cattle and has also been found to cause the majority of reported human infections in Sweden during the past 15 years. In most calves, inoculated with a representative strain of this specific subtype, the numbers of shed bacteria declined over the first two weeks. One calf could possibly be classified as a high-shedder, excreting high levels of the bacterium for a prolonged period.</p

Prognostic model to predict postoperative acute kidney injury in patients undergoing major gastrointestinal surgery based on a national prospective observational cohort study.

Background: Acute illness, existing co-morbidities and surgical stress response can all contribute to postoperative acute kidney injury (AKI) in patients undergoing major gastrointestinal surgery. The aim of this study was prospectively to develop a pragmatic prognostic model to stratify patients according to risk of developing AKI after major gastrointestinal surgery. Methods: This prospective multicentre cohort study included consecutive adults undergoing elective or emergency gastrointestinal resection, liver resection or stoma reversal in 2-week blocks over a continuous 3-month period. The primary outcome was the rate of AKI within 7 days of surgery. Bootstrap stability was used to select clinically plausible risk factors into the model. Internal model validation was carried out by bootstrap validation. Results: A total of 4544 patients were included across 173 centres in the UK and Ireland. The overall rate of AKI was 14·2 per cent (646 of 4544) and the 30-day mortality rate was 1·8 per cent (84 of 4544). Stage 1 AKI was significantly associated with 30-day mortality (unadjusted odds ratio 7·61, 95 per cent c.i. 4·49 to 12·90; P < 0·001), with increasing odds of death with each AKI stage. Six variables were selected for inclusion in the prognostic model: age, sex, ASA grade, preoperative estimated glomerular filtration rate, planned open surgery and preoperative use of either an angiotensin-converting enzyme inhibitor or an angiotensin receptor blocker. Internal validation demonstrated good model discrimination (c-statistic 0·65). Discussion: Following major gastrointestinal surgery, AKI occurred in one in seven patients. This preoperative prognostic model identified patients at high risk of postoperative AKI. Validation in an independent data set is required to ensure generalizability