Level-1 pixel based tracking trigger algorithm for LHC upgrade

The Pixel Detector is the innermost detector of the tracking system of the Compact Muon Solenoid (CMS) experiment at CERN Large Hadron Collider (LHC). It precisely determines the interaction point (primary vertex) of the events and the possible secondary vertexes due to heavy flavours ($b$ and $c$ quarks); it is part of the overall tracking system that allows reconstructing the tracks of the charged particles in the events and combined with the magnetic field to measure their impulsion. The pixel detector allows measuring the tracks in the region closest to the interaction point. The Level-1 (real-time) pixel based tracking trigger is a novel trigger system that is currently being studied for the LHC upgrade. An important goal is developing real-time track reconstruction algorithms able to cope with very high rates and high flux of data in a very harsh environment. The pixel detector has an especially crucial role in precisely identifying the primary vertex of the rare physics events from the large pile-up (PU) of events. The goal of adding the pixel information already at the real-time level of the selection is to help reducing the total level-1 trigger rate while keeping an high selection capability. This is quite an innovative and challenging objective for the experiments upgrade for the High Luminosity LHC (HL-LHC). The special case here addressed is the CMS experiment. This document describes exercises focusing on the development of a fast pixel track reconstruction where the pixel track matches with a Level-1 electron object using a ROOT-based simulation framework.Comment: Submitted to JINST; 12 pages, 10 figures, Contribution to the JINST proceedings for the INFIERI2014 School in Paris, France, July 14-25, 201

Overview of the SiLC R&D Activities

The R&D Collaboration SiLC (Silicon tracking for Linear Colliders) is based on generic R&D aiming to develop the next generation of large Silicon tracking systems for the Linear collider experiments; it serves all three ILC detector concepts. There is a strong involvement in ILD, a natural collaboration with SiD and recent 4th concept interest to use Silicon tracking technology as well. Here is a very brief summary of the latest results on sensors, Front End Electronics, Mechanics and Integration issues, test bench and test beam results and where to go from there.Comment: 3 pages, 3 figures, LCWS08 Worksho

Large Silicon Tracking Systems for ILC: Role, Design and Main issues

The roles, the designs, the main issues and the current status of the R&D on large Silicon Tracking Systems for the ILC are discussed in this paper. The R&D work presented here is performed within the SiLC (Silicon tracking for the Linear Collider) R&D Collaboration

A new 130nm F.E readout chip for microstrip detectors

In the context of the Silicon tracking for a Linear Collider (SiLC) R&D collaboration, a highly compact mixed-signal chip has been designed in 130nm CMOS technology intended to read Silicon strip detectors for the experiments at the future International Linear Collider. The chip includes eighty eight channels of a full analog signal processing chain and analog to digital conversion with the corresponding digital controls and readout channels. The chip is 5x10mm2 where the analog implementation represents 4/5 of the total Silicon area.Comment: 3 pages, 4 figures, LCWS08 worksho

Silicon Data Acquisition and Front-End Electronics

A highly integrated Front-End readout and Data Acquisition scheme for Silicon trackers is presented. In this context, a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, having in view a highly multiplexed and sparsified readout global strategy. First results are presented

Large Area Silicon Tracking: New Perspectives

The successful running of the large area Silicon trackers of ATLAS and CMS at LHC, and the ongoing R&D for the upgrade of these tracking systems, in various stages, over this decade, are a full proof of this technology and of its still impressive potential. The Linear Collider project is waiting for the possible discovery of a light Higgs at LHC maybe by end of 2012. These facts opened a new phase for the R&D on Silicon tracking for the Linear Collider, with enhanced synergy with LHC, Astrophysics and other HEP experiments, thus leading to new perspectives and alternatives.Comment: LCWS2011 Proceedings, 10 page

Front-End and Readout Electronics for Silicon Trackers at the ILC

A highly integrated readout scheme for Silicon trackers making use of Deep Sub-Micron CMOS electronics is presented. In this context,a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, each channel comprising a low noise amplifier, a pulse shaper, a sample and hold and a comparator. First results are presented

Front-end Electronics for Silicon Trackers readout in Deep Sub-Micron CMOS Technology: The case of Silicon strips at the ILC

For the years to come, Silicon strips detectors will be read using the smallest available integrated technologies for room, transparency, and power considerations. CMOS, Bipolar- CMOS and Silicon-Germanium are presently offered in deepsubmicron (250 down to 90nm) at affordable cost through worldwide integrated circuits multiproject centers. As an example, a 180nm CMOS readout prototype chip has been designed and tested, and gave satisfactory results in terms of noise and power. Beam tests are under work, and prospectives in 130nm will be presented

Searches for Physics Beyond the Standard Model at Colliders

All experimental measurements of particle physics today are beautifully described by the Standard Model. However, there are good reasons to believe that new physics may be just around the corner at the TeV energy scale. This energy range is currently probed by the Tevatron and HERA accelerators and selected results of searches for physics beyond the Standard Model are presented here. No signals for new physics have been found and limits are placed on the allowed parameter space for a variety of different particles.Comment: Proceedings for 2007 Europhysics Conference on High Energy Physics, Manchester, July 200

A CMOS 130nm Evaluation digitzer chip for silicon strips readout

A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power