A Novel Algorithm to Detect and Transmit Human-Directed Signboard Image Text to Vehicle Using 5G-Enabled Wireless Networks

The emerging 5G telecommunication technology uses novel aspects to fulfill the challenges of high data rate, ultra-low latency, broad bandwidth with the best user experience for text detection in sign board and thereafter transmission of identified information to the vehicles. This is performed on the images which are amorphous in nature or containing scenarios which are random or that cannot be determined. Detecting and transmission of textsover 5G wireless network from the unstructured images aids in many of the additional applications like Optical Character Recognition (OCR) and 5G technolog such as an eMBB, mMTC, and URLLC for quality of service and customer satisfaction.This approach can be used to alert a driver about any road sign even from a captured video by using 5G wireless network irrespective of the weathercondition or any obstacle which may make sign boards difficult to see for drivers. The algorithm uses Maximally Stable Extremal Regions (MSER) feature detector. The algorithm contains several steps which are briefly described in the paper.</p

An Energy Dissipation and Cell Optimization of Vedic Multiplier Topologies for Nanocomputing Applications

Quantum-dot cellular automata is a cutting edge enumeration methodology that suggests less area and high speedcompare CMOS methodology. The CMOS circuitry having issues related to short channel and device density so QCA is betterand powerful alternative to reduce the area as well as increase the speed of the circuitry. QCA could be a modern computinginnovation that’s made of quantum cell containing two electrons and dots. A multiplier is a vital part of Digital SignalProcessing (DSP) and many more digital circuits applications. We emphasize Vedic multiplier topologies structures agreeingto Vedic science from old Indian figures. In this article, we suggested a efficient, less complex Vedic 22 and 44 multiplierstopologies using proposed ultra efficient Half Adder (HA), Full Adder (FA) topologies in QCADesigner simulationenvironment for less energy and fast speed for nano computing application. The simulation waveform suggests an architectureoutstrip in comparison to the parameters of cell count, area, latency related to past QCA layouts. The proposed QCA 22Vedic multiplier design shown 37.62% improvement in QCA cell count and 44 Vedic multiplier design shown 71.72%improvement in cell counts as well as 29.62% area is decreased for 22 QCA Vedic multiplier and 43.38% area decreasedfrom 4 4 QCA Vedic multiplier as related to its best existing designs