A simulation-based performance evaluation of anti-collision protocols for RFID system

RFID is being widely employed in a variety of applications. Anti-collision protocol has a major influence on improving the system identification efficiency for RFID system. In this paper, we propose a simulation-based method to evaluate the anti-collision algorithm performance of GJB protocol. According to the assessment result, the system parameters are confirmed to optimize design. As a part of the reference model, the early evaluation model reuses in the functional verification by filling details to reduce the verification cost. ? 2014 IEEE.EI

A verification methodology for reusable test cases and coverage based on system verilog

As the size and complexity of SoC design grow, it is common to establish a scalable and reusable verification test bench for verification engineers. To improve the efficiency of verification and reduce the development time and effort in chip design projects, the extensive and reusable test case model and function coverage model for the special circuit and the standard protocols should be focused on by verification engineers. In this paper, a verification methodology for reusable test cases and coverage is described. As an example, a reusable test bench of chain table DUT is utilized to verify the feasibility of the verification methodology. ? 2014 IEEE.EI

K-band micro-strip antenna array applied in anti-collision radar

A K-band micro-strip array double-antenna applied in 24GHz automotive collision warning radar is presented in this paper. The double-antenna consists of two individual 14??6 elements arrays which both are placed on ROGERS RT5880 substrate with 0.254 mm thickness, one for the transmitter (TX) and one for the receiver (RX). The results of simulation show that the double-antenna has gain of 26.5dB and efficiency of 60%, the -10dB bandwidth is 1GHz from 23.6GHz to 24.6GHz, three-decibel beamwidth in azimuth is 6?? and in elevation is 18??, the sub lobe suppression in azimuth is better than -20dB and in elevation is better than -15dB. The isolation between two antennas array is better than -32dB. ? 2010 IEEE.EI

A three-stage LDO with active feedback frequency compensation and slew-rate enhancement

This paper presents a low drop-out (LDO) regulator using an active feedback frequency compensation (AFFC) structure for compensation. By eliminating the right-half-plane zero and bringing a left one, the phase margin and the stability can be improved. And the compensation loop reuses the current in the first stage to minimize the quiescent current. A slew-rate enhancement circuit is presented to speed up transient response. The LDO regulator provides full range stability from 0 to 100mA load current. The LDO is simulated in a 0.18um CMOS process, supplying 1.6V with a dropout voltage of 181mV. The quiescent current is 29uA for 100pF load capacitor.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000341774100208&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701CPCI-S(ISTP)

Scheduling to timing optimization for a novel high-level synthesis approach

Traditional IC design methodology based on standard cells shows its limitation on design efficiency, which can not satisfy the needs for shorter time-to-market and more advanced functionality of IC products. To solve this problem, a novel high level synthesis method named operator design method is proposed. In this paper, a scheduling scheme to timing optimization for operator design method is proposed, which is carried out based on the attributes of the operand in the operation and dependence of the operations. The experiment results proves the feasibility and the efficiency of the operator design method, and obtains a 65% faster data-processing capacity and 30% reduction in hardware cost than that of SPARK tool of University California at San Diego. ? 2011 IEEE.EI

Implementation of intra prediction in H.264 based on a novel design methodology

A novel IC design methodology, named Operator Methodology (OM), is proposed in this paper and has been applied to intra prediction of H.264 entropy coding, satisfying the need of 1080P@30pfs performance. This new methodology will map the high-level language, such as C programming language, to verilog HDL through a special middle language, using a series of analysis processes like time-noting and optimization. The implementation of intra prediction in H.264 by OM, which is verified to work at 100MHZ in a Xilinx Virtex6 FPGA and 0.13um SMIC CMOS technology at 167MHz frequency, shows that OM can speed up IC design effectively and obtain comparable performance with other ASIC results. Finally, our design cycle, measured by man-month, will be decreased by a large scale using auto-translator and auto-optimizer. ? 2011 IEEE.EI